drivers/crypto/intel/qat/qat_common/qat_hal.c

310

SET_CAP_CSR(handle, reset_csr, csr_val);

drivers/crypto/intel/qat/qat_common/qat_hal.c

427

SET_CAP_CSR(handle, misc_ctl_csr, misc_ctl &

drivers/crypto/intel/qat/qat_common/qat_hal.c

435

SET_CAP_CSR(handle, misc_ctl_csr, misc_ctl | MC_TIMESTAMP_ENABLE);

drivers/crypto/intel/qat/qat_common/qat_hal.c

487

SET_CAP_CSR(handle, reset_csr, csr_val);

drivers/crypto/intel/qat/qat_common/qat_hal.c

496

SET_CAP_CSR(handle, clk_csr, csr_val);

drivers/crypto/intel/qat/qat_common/qat_hal.c

906

SET_CAP_CSR(handle, fcu_ctl_csr, FCU_CTRL_CMD_START);

drivers/crypto/intel/qat/qat_common/qat_uclo.c

1246

SET_CAP_CSR(handle, fcu_dram_hi_csr, bus_addr >> BITS_PER_TYPE(u32));

drivers/crypto/intel/qat/qat_common/qat_uclo.c

1247

SET_CAP_CSR(handle, fcu_dram_lo_csr, bus_addr);

drivers/crypto/intel/qat/qat_common/qat_uclo.c

1248

SET_CAP_CSR(handle, fcu_ctl_csr, FCU_CTRL_CMD_AUTH);

drivers/crypto/intel/qat/qat_common/qat_uclo.c

1311

SET_CAP_CSR(handle, FCU_ME_BROADCAST_MASK_TYPE,

drivers/crypto/intel/qat/qat_common/qat_uclo.c

1314

SET_CAP_CSR(handle, fcu_ctl_csr, FCU_CTRL_CMD_LOAD);

drivers/crypto/intel/qat/qat_common/qat_uclo.c

1692

SET_CAP_CSR(handle, fcu_ctl_csr,