drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

140

retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

298

uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET +

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

135

retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

321

uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET +

drivers/gpu/drm/amd/amdgpu/cik.c

1053

{mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET},

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

1073

tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

1075

WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

1125

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

1127

WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

1130

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

1132

WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

50

SDMA1_REGISTER_OFFSET

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

879

WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

886

orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

889

WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

904

orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

907

WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

914

orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

917

WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

1019

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

1021

WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

1024

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

1026

WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

61

SDMA1_REGISTER_OFFSET

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

966

tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

968

WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

1357

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

1359

WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

1362

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

1364

WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

76

SDMA1_REGISTER_OFFSET

drivers/gpu/drm/amd/amdgpu/vi.c

676

{mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET},

drivers/gpu/drm/radeon/cik.c

166

case (SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET):

drivers/gpu/drm/radeon/cik.c

3328

WREG32(SDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70);

drivers/gpu/drm/radeon/cik.c

4814

RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET));

drivers/gpu/drm/radeon/cik.c

4871

tmp = RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/radeon/cik.c

4960

tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/radeon/cik.c

4962

WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);

drivers/gpu/drm/radeon/cik.c

5161

tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/radeon/cik.c

5163

WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);

drivers/gpu/drm/radeon/cik.c

5514

WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA1_REGISTER_OFFSET, 0);

drivers/gpu/drm/radeon/cik.c

5515

WREG32(SDMA0_GFX_APE1_CNTL + SDMA1_REGISTER_OFFSET, 0);

drivers/gpu/drm/radeon/cik.c

6160

WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);

drivers/gpu/drm/radeon/cik.c

6167

orig = data = RREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/radeon/cik.c

6170

WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);

drivers/gpu/drm/radeon/cik.c

6185

orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/radeon/cik.c

6188

WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);

drivers/gpu/drm/radeon/cik.c

6195

orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/radeon/cik.c

6198

WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);

drivers/gpu/drm/radeon/cik.c

6865

tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;

drivers/gpu/drm/radeon/cik.c

6866

WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp);

drivers/gpu/drm/radeon/cik.c

7049

dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;

drivers/gpu/drm/radeon/cik.c

7220

WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, dma_cntl1);

drivers/gpu/drm/radeon/cik_sdma.c

118

reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET;

drivers/gpu/drm/radeon/cik_sdma.c

262

reg_offset = SDMA1_REGISTER_OFFSET;

drivers/gpu/drm/radeon/cik_sdma.c

312

reg_offset = SDMA1_REGISTER_OFFSET;

drivers/gpu/drm/radeon/cik_sdma.c

344

reg_offset = SDMA1_REGISTER_OFFSET;

drivers/gpu/drm/radeon/cik_sdma.c

379

reg_offset = SDMA1_REGISTER_OFFSET;

drivers/gpu/drm/radeon/cik_sdma.c

492

WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);

drivers/gpu/drm/radeon/cik_sdma.c

494

WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, le32_to_cpup(fw_data++));

drivers/gpu/drm/radeon/cik_sdma.c

495

WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);

drivers/gpu/drm/radeon/cik_sdma.c

508

WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);

drivers/gpu/drm/radeon/cik_sdma.c

510

WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, be32_to_cpup(fw_data++));

drivers/gpu/drm/radeon/cik_sdma.c

511

WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);

drivers/gpu/drm/radeon/cik_sdma.c

515

WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);

drivers/gpu/drm/radeon/cik_sdma.c

73

reg = SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET;

drivers/gpu/drm/radeon/cik_sdma.c

97

reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET;