Symbol: SDMA0_CNTL
drivers/gpu/drm/amd/amdgpu/cik_sdma.c
372
f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
drivers/gpu/drm/amd/amdgpu/cik_sdma.c
381
f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
1004
sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
1009
sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
1020
sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
1025
sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
1342
sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
1347
sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
1358
sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
1363
sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
580
f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
582
f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
591
f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
593
f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
1011
f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
1414
temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
2079
sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
1608
cntl = REG_SET_FIELD(cntl, SDMA0_CNTL, UTC_L1_ENABLE, 0);
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
1694
sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
629
f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
793
temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
796
temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
1520
cntl = REG_SET_FIELD(cntl, SDMA0_CNTL, UTC_L1_ENABLE, 0);
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
1603
sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
488
f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
640
temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
643
temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
1622
sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
438
f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
1554
sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
drivers/gpu/drm/radeon/cik.c
6863
tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
drivers/gpu/drm/radeon/cik.c
6864
WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp);
drivers/gpu/drm/radeon/cik.c
6865
tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
drivers/gpu/drm/radeon/cik.c
6866
WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp);
drivers/gpu/drm/radeon/cik.c
7048
dma_cntl = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
drivers/gpu/drm/radeon/cik.c
7049
dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
drivers/gpu/drm/radeon/cik.c
7219
WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl);
drivers/gpu/drm/radeon/cik.c
7220
WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, dma_cntl1);
drivers/gpu/drm/radeon/cik_sdma.c
313
value = RREG32(SDMA0_CNTL + reg_offset);
drivers/gpu/drm/radeon/cik_sdma.c
318
WREG32(SDMA0_CNTL + reg_offset, value);