SEND
return REGB_POLL_FLD(VPU_HW_BTRS_MTL_WP_REQ_CMD, SEND, 0, PLL_TIMEOUT_US);
return REGB_POLL_FLD(VPU_HW_BTRS_LNL_WP_REQ_CMD, SEND, 0, PLL_TIMEOUT_US);
val = REG_SET_FLD(VPU_HW_BTRS_MTL_WP_REQ_CMD, SEND, val);
val = REG_SET_FLD(VPU_HW_BTRS_LNL_WP_REQ_CMD, SEND, val);
HR_OPC_MAP(SEND, SEND),
HR_WC_OP_MAP(SEND, SEND),
HR_WC_OP_MAP(SEND_WITH_INV, SEND),
HR_WC_OP_MAP(SEND_WITH_IMM, SEND),
HR_WC_OP_MAP(SEND, RECV),
wqe->base.op = IONIC_OP(dev->lif_cfg.rdma_version, SEND);
wqe->base.op = IONIC_OP(dev->lif_cfg.rdma_version, SEND);
wc_opcode_name(SEND), \
wr_opcode_name(SEND), \
writel((bank << BANK_SHIFT) | SEND | TFIE | (bytes << TX_LEN_SHIFT),
val = (bank << BANK_SHIFT) | SEND | (1 << TX_LEN_SHIFT) |
ipw_hdr->host_command_reg = SEND;
if (uap->rs485_tx_state == SEND)
uap->rs485_tx_state = SEND;
uap->rs485_tx_state = SEND;
uap->rs485_tx_state = SEND;
uap->rs485_tx_state != SEND) {
if (sport->tx_state == WAIT_AFTER_RTS || sport->tx_state == SEND)
if (sport->tx_state == SEND) {
sport->tx_state = SEND;
sport->tx_state = SEND;
struct ext_wait_queue *sender = wq_get_first_waiter(info, SEND);
ret = wq_sleep(info, SEND, timeout, &wait);
DECLARE_PRIMITIVE(SEND);