arch/m68k/68000/dragen2.c

45

SCR = 0x10; /* allow user access to internal registers */

drivers/gpu/drm/stm/lvds.c

179

u32 SCR; /* Serial Control Register */

drivers/gpu/drm/stm/lvds.c

209

.SCR = 0x20,

drivers/gpu/drm/stm/lvds.c

235

.SCR = 0x20,

drivers/gpu/drm/stm/lvds.c

370

lvds_set(lvds, phy->base + phy->ofs.SCR, PHY_SCR_TX_EN);

drivers/net/wan/hdlc_ppp.c

278

{IRC|SCR|3, INV , INV , INV , INV , INV , INV }, /* START */

drivers/net/wan/hdlc_ppp.c

280

{ INV , INV ,STR|2, SCR|3 ,SCR|3, SCR|5 , INV }, /* TO+ */

drivers/net/wan/hdlc_ppp.c

282

{ STA|0 ,IRC|SCR|SCA|5, 2 , SCA|5 ,SCA|6, SCA|5 ,SCR|SCA|5}, /* RCR+ */

drivers/net/wan/hdlc_ppp.c

283

{ STA|0 ,IRC|SCR|SCN|3, 2 , SCN|3 ,SCN|4, SCN|3 ,SCR|SCN|3}, /* RCR- */

drivers/net/wan/hdlc_ppp.c

284

{ STA|0 , STA|1 , 2 , IRC|4 ,SCR|3, 6 , SCR|3 }, /* RCA */

drivers/net/wan/hdlc_ppp.c

285

{ STA|0 , STA|1 , 2 ,IRC|SCR|3,SCR|3,IRC|SCR|5, SCR|3 }, /* RCN */

drivers/net/wan/hdlc_ppp.c

287

{ 0 , 1 , 1 , 3 , 3 , 5 , SCR|3 }, /* RTA */

drivers/net/wan/hdlc_ppp.c

316

if (action & (SCR | STR)) /* set Configure-Req/Terminate-Req timer */

drivers/net/wan/hdlc_ppp.c

325

if (action & SCR) /* send Configure-Request */

drivers/scsi/lpfc/lpfc_els.c

3571

cmdsize = (sizeof(uint32_t) + sizeof(SCR));

drivers/scsi/lpfc/lpfc_els.c

3602

memset(pcmd, 0, sizeof(SCR));

drivers/scsi/lpfc/lpfc_els.c

3603

((SCR *) pcmd)->Function = SCR_FUNC_FULL;

drivers/scsi/lpfc/lpfc_hw.h

1099

SCR scr; /* Payload for SCR/ACC */

drivers/video/fbdev/imsttfb.c

740

write_reg_le32(par->dc_regs, SCR, scr);