drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

345

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

429

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

431

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

432

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

449

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

458

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

521

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

669

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

671

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

672

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

690

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

728

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1071

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1073

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1074

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1113

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1153

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

929

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, enable ? 1 : 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

570

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

707

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

709

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

710

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

747

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

822

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

420

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

556

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

558

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

559

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

597

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

669

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);

drivers/gpu/drm/radeon/cik_sdma.c

263

rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset);

drivers/gpu/drm/radeon/cik_sdma.c

265

WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);

drivers/gpu/drm/radeon/cik_sdma.c

392

WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);

drivers/gpu/drm/radeon/cik_sdma.c

414

WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE);