SCLK_VOP0_PWM
GATE(SCLK_VOP0_PWM, "sclk_vop0_pwm", "xin24m", 0,
COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, 0,