SCR
SCR = 0x10; /* allow user access to internal registers */
u32 SCR; /* Serial Control Register */
.SCR = 0x20,
.SCR = 0x20,
lvds_set(lvds, phy->base + phy->ofs.SCR, PHY_SCR_TX_EN);
outb(0x5a, SCR(iobase));
b1 = inb(SCR(iobase));
outb(0xa5, SCR(iobase));
b2 = inb(SCR(iobase));
outb(0x5a, SCR(iobase));
b1 = inb(SCR(iobase));
outb(0xa5, SCR(iobase));
b2 = inb(SCR(iobase));
outb(0x5a, SCR(iobase));
b1 = inb(SCR(iobase));
outb(0xa5, SCR(iobase));
b2 = inb(SCR(iobase));
{IRC|SCR|3, INV , INV , INV , INV , INV , INV }, /* START */
{ INV , INV ,STR|2, SCR|3 ,SCR|3, SCR|5 , INV }, /* TO+ */
{ STA|0 ,IRC|SCR|SCA|5, 2 , SCA|5 ,SCA|6, SCA|5 ,SCR|SCA|5}, /* RCR+ */
{ STA|0 ,IRC|SCR|SCN|3, 2 , SCN|3 ,SCN|4, SCN|3 ,SCR|SCN|3}, /* RCR- */
{ STA|0 , STA|1 , 2 , IRC|4 ,SCR|3, 6 , SCR|3 }, /* RCA */
{ STA|0 , STA|1 , 2 ,IRC|SCR|3,SCR|3,IRC|SCR|5, SCR|3 }, /* RCN */
{ 0 , 1 , 1 , 3 , 3 , 5 , SCR|3 }, /* RTA */
if (action & (SCR | STR)) /* set Configure-Req/Terminate-Req timer */
if (action & SCR) /* send Configure-Request */
cmdsize = (sizeof(uint32_t) + sizeof(SCR));
memset(pcmd, 0, sizeof(SCR));
((SCR *) pcmd)->Function = SCR_FUNC_FULL;
SCR scr; /* Payload for SCR/ACC */
unsigned short val = rd_reg16(info, SCR);
wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
wr_reg16(info, SCR,
(unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
wr_reg16(info, SCR, val);
wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
write_reg_le32(par->dc_regs, SCR, scr);