drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

144

REG_SET(SCL_CONTROL, 0, SCL_BOUNDARY_MODE, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.h

227

XFM_SF(SCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh), \

drivers/gpu/drm/amd/display/dc/dce/dce_transform.h

397

XFM_SF(SCL0_SCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh), \

drivers/gpu/drm/amd/display/dc/dce/dce_transform.h

489

type SCL_BOUNDARY_MODE; \

drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c

212

set_reg_field_value(value, 1, SCLV_CONTROL, SCL_BOUNDARY_MODE);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

213

TF_SF(DSCL0_DSCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh),\

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

500

type SCL_BOUNDARY_MODE; \

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

643

SCL_BOUNDARY_MODE, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

240

TF_SF(DSCL0_DSCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh),\

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

85

TF_SF(DSCL0_DSCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh),\

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1113

SCL_BOUNDARY_MODE, 0);