SCLK_UART5
GATE(SCLK_UART5, "clk_uart5", "clk_uart5_mux", CLK_SET_RATE_PARENT,
COMPOSITE(SCLK_UART5, "sclk_uart5", sclk_uart_parents_p, 0,
GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0,
GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0,
GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 0,
COMPOSITE(SCLK_UART5, "sclk_uart5", clk_uart_p, 0,
GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0,
GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 0,
COMPOSITE(SCLK_UART5, "sclk_uart5", mux_sclk_uart_src_p, 0,