SCLK_UART4
GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", CLK_SET_RATE_PARENT,
MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT,
GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", 0,
MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT,
COMPOSITE(SCLK_UART4, "sclk_uart4", sclk_uart_parents_p, 0,
GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0,
GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0,
GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 0,
COMPOSITE(SCLK_UART4, "sclk_uart4", clk_uart_p, 0,
GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0,
GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 0,
COMPOSITE(SCLK_UART4, "sclk_uart4", mux_sclk_uart_src_p, 0,