SCLK_UART3
GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", CLK_SET_RATE_PARENT,
MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, CLK_SET_RATE_PARENT,
MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", 0,
MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
MUX(SCLK_UART3, "clk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
COMPOSITE(SCLK_UART3, "sclk_uart3", sclk_uart_parents_p, 0,
GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0,
GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0,
GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 0,
COMPOSITE(SCLK_UART3, "sclk_uart3", clk_uart_p, 0,
GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0,
GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 0,
COMPOSITE(SCLK_UART3, "sclk_uart3", mux_sclk_uart_src_p, 0,
GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user",
GATE(SCLK_UART3, "sclk_uart3", "dout_uart3", CLK_SRC_MASK0, 15,