SCLK_UART1
GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", CLK_SET_RATE_PARENT,
MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, CLK_SET_RATE_PARENT,
MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", 0,
MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
MUX(SCLK_UART1, "clk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
COMPOSITE(SCLK_UART1, "sclk_uart1", sclk_uart_parents_p, 0,
GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0,
GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0,
GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 0,
COMPOSITE_NODIV(SCLK_UART1, "sclk_uart1", uart1_p, 0,
GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0,
MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 0,
COMPOSITE(SCLK_UART1, "sclk_uart1", mux_sclk_uart_src_p, 0,
GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user",
GATE(SCLK_UART1, "sclk_uart1", "dout_uart1", CLK_SRC_MASK0, 13,