SCLK_TIMER0
GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
COMPOSITE_NODIV(SCLK_TIMER0, "sclk_timer0", mux_timer_p, CLK_IGNORE_UNUSED,
GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
GATE(SCLK_TIMER0, "timer0", "xin24m", 0, RK2928_CLKGATE_CON(1), 0, GFLAGS),
GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
GATE(SCLK_TIMER0, "clk_timer0", "xin24m", 0,