SCLK_PWM
COMPOSITE(SCLK_PWM, "clk_pwm", mux_2plls_p, 0,
COMPOSITE(SCLK_PWM, "clk_pwm", mux_pll_src_2plls_p, 0,
GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0),
GATE(SCLK_PWM, "sclk_pwm", "dout_pwm", CLK_SRC_MASK0, 19,