SCLK_AUDPWM
MUX(SCLK_AUDPWM, "sclk_audpwm", sclk_audpwm_p, CLK_SET_RATE_PARENT,
GATE(SCLK_AUDPWM, "sclk_audpwm", "mclk_audpwm_mux", 0,