arch/powerpc/xmon/ppc-opc.c

2498

#define SCI8_MASK SCI8(0x3f, 0x1f)

arch/powerpc/xmon/ppc-opc.c

7014

{"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},

arch/powerpc/xmon/ppc-opc.c

7015

{"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},

arch/powerpc/xmon/ppc-opc.c

7016

{"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},

arch/powerpc/xmon/ppc-opc.c

7017

{"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},

arch/powerpc/xmon/ppc-opc.c

7018

{"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},

arch/powerpc/xmon/ppc-opc.c

7019

{"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},

arch/powerpc/xmon/ppc-opc.c

7020

{"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},

arch/powerpc/xmon/ppc-opc.c

7021

{"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},

arch/powerpc/xmon/ppc-opc.c

7022

{"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},

arch/powerpc/xmon/ppc-opc.c

7023

{"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},

arch/powerpc/xmon/ppc-opc.c

7024

{"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},

arch/powerpc/xmon/ppc-opc.c

7025

{"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},

arch/powerpc/xmon/ppc-opc.c

7026

{"e_nop", SCI8(6,26), 0xffffffff, PPCVLE, 0, {0}},

arch/powerpc/xmon/ppc-opc.c

7027

{"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},

arch/powerpc/xmon/ppc-opc.c

7028

{"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},

arch/powerpc/xmon/ppc-opc.c

7029

{"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},

arch/powerpc/xmon/ppc-opc.c

7030

{"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},