SCDL
if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
sci_serial_out(port, SCDL, dl);
if (sci_getreg(port, SCDL)->size)
regs->scdl = sci_serial_in(port, SCDL);
if (sci_getreg(port, SCDL)->size)
sci_serial_out(port, SCDL, regs->scdl);
[SCDL] = { 0x30, 16 },
[SCDL] = { 0x30, 16 },