S3
S3(r3, r4, r0, r1, r2); store_and_load_keys(r1, r2, r4, r3, 28, 24);
S3(r2, r4, r3, r0, r1); store_and_load_keys(r0, r1, r4, r2, -4, -8);
S3(r1, r4, r2, r3, r0); store_and_load_keys(r3, r0, r4, r1, 14, 10);
S3(r0, r4, r1, r2, r3); store_and_load_keys(r2, r3, r4, r0, -18, -22);
S3(r3, r4, r0, r1, r2); storekeys(r1, r2, r4, r3, 0);
S3(r1, r3, r4, r2, r0); LK(r2, r0, r3, r1, r4, 4);
S3(r0, r3, r1, r4, r2); LK(r4, r2, r3, r0, r1, 12);
S3(r2, r3, r0, r1, r4); LK(r1, r4, r3, r2, r0, 20);
S3(r4, r3, r2, r0, r1); LK(r0, r1, r3, r4, r2, 28);
#define NS3(T1, S1, T2, S2, T3, S3) \
val.T2 = (S2); val.T3 = (S3); val; })
#define _NS3(D, T1, S1, T2, S2, T3, S3) \
__ns.T2 = (S2); __ns.T3 = (S3); __ns; })
#define S(s, v) S3("s", s, v)
#define T3(fmt_spec, s, v) S3(fmt_spec, s, tx[i].v)
#define T(s, v) S3("u", s, tx[i].v)
#define R3(fmt_spec, s, v) S3(fmt_spec, s, rx[i].v)
#define R(s, v) S3("u", s, rx[i].v)
S3("u", "DCB PGID:",
S3("u", "DCB PFC:",
S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq));
S3("u", "Intr pktcnt:", s->counter_val[rx[i].rspq.pktcnt_idx]);
S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq));
S3("u", "Intr pktcnt:", s->counter_val[rx[i].rspq.pktcnt_idx]);
S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq));
S3("u", "Intr pktcnt:", s->counter_val[rx[i].rspq.pktcnt_idx]);
S3("u", "FL size:", rx->fl.size ? rx->fl.size - 8 : 0);
S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq));
S3("u", "Intr pktcnt:", s->counter_val[rx[i].rspq.pktcnt_idx]);
S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq));
S3("u", "Intr pktcnt:", s->counter_val[rx[i].rspq.pktcnt_idx]);
S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq));
S3("u", "Intr pktcnt:", s->counter_val[rx[i].rspq.pktcnt_idx]);
S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq));
S3("u", "Intr pktcnt:", s->counter_val[rx[i].rspq.pktcnt_idx]);
S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq));
S3("u", "Intr pktcnt:", s->counter_val[rx[i].rspq.pktcnt_idx]);
S3("u", "Intr delay:", qtimer_val(adap, &rx[i].rspq));
S3("u", "Intr pktcnt:", s->counter_val[rx[i].rspq.pktcnt_idx]);
#define S(s, v) S3("s", s, v)
#define T(s, v) S3("u", s, txq[qs].v)
#define R(s, v) S3("u", s, rxq[qs].v)
S3("d", "Port:",
S3("u", "Intr delay:", qtimer_val(adapter, &rxq[qs].rspq));
S3("u", "Intr pktcnt:",
#define S(s, v) S3("s", s, v)
#define T3(fmt, s, v) S3(fmt, s, txq[qs].v)
#define R3(fmt, s, v) S3(fmt, s, rxq[qs].v)
{ PCI_VDEVICE(S3, 0x8810), .driver_data = CHIP_XXX_TRIO },
{ PCI_VDEVICE(S3, 0x8811), .driver_data = CHIP_XXX_TRIO },
{ PCI_VDEVICE(S3, 0x8812), .driver_data = CHIP_M65_AURORA64VP },
{ PCI_VDEVICE(S3, 0x8814), .driver_data = CHIP_767_TRIO64UVP },
{ PCI_VDEVICE(S3, 0x8901), .driver_data = CHIP_XXX_TRIO64V2_DXGX },
{ PCI_VDEVICE(S3, 0x8902), .driver_data = CHIP_551_PLATO_PX },
{ PCI_VDEVICE(S3, 0x5631), .driver_data = CHIP_325_VIRGE },
{ PCI_VDEVICE(S3, 0x883D), .driver_data = CHIP_988_VIRGE_VX },
{ PCI_VDEVICE(S3, 0x8A01), .driver_data = CHIP_XXX_VIRGE_DXGX },
{ PCI_VDEVICE(S3, 0x8A10), .driver_data = CHIP_357_VIRGE_GX2 },
{ PCI_VDEVICE(S3, 0x8A11), .driver_data = CHIP_359_VIRGE_GX2P },
{ PCI_VDEVICE(S3, 0x8A12), .driver_data = CHIP_359_VIRGE_GX2P },
{ PCI_VDEVICE(S3, 0x8A13), .driver_data = CHIP_36X_TRIO3D_1X_2X },
{ PCI_VDEVICE(S3, 0x8904), .driver_data = CHIP_365_TRIO3D },
{ PCI_VDEVICE(S3, 0x8C01), .driver_data = CHIP_260_VIRGE_MX },
PCI_VDEVICE(S3, PCI_CHIP_SUPSAV_MX128),
PCI_VDEVICE(S3, PCI_CHIP_SUPSAV_MX64),
PCI_VDEVICE(S3, PCI_CHIP_SUPSAV_MX64C),
PCI_VDEVICE(S3, PCI_CHIP_SUPSAV_IX128SDR),
PCI_VDEVICE(S3, PCI_CHIP_SUPSAV_IX128DDR),
PCI_VDEVICE(S3, PCI_CHIP_SUPSAV_IX64SDR),
PCI_VDEVICE(S3, PCI_CHIP_SUPSAV_IX64DDR),
PCI_VDEVICE(S3, PCI_CHIP_SUPSAV_IXCSDR),
PCI_VDEVICE(S3, PCI_CHIP_SUPSAV_IXCDDR),
PCI_VDEVICE(S3, PCI_CHIP_SAVAGE4),
PCI_VDEVICE(S3, PCI_CHIP_SAVAGE3D),
PCI_VDEVICE(S3, PCI_CHIP_SAVAGE3D_MV),
PCI_VDEVICE(S3, PCI_CHIP_SAVAGE2000),
PCI_VDEVICE(S3, PCI_CHIP_SAVAGE_MX_MV),
PCI_VDEVICE(S3, PCI_CHIP_SAVAGE_MX),
PCI_VDEVICE(S3, PCI_CHIP_SAVAGE_IX_MV),
PCI_VDEVICE(S3, PCI_CHIP_SAVAGE_IX),
PCI_VDEVICE(S3, PCI_CHIP_PROSAVAGE_PM),
PCI_VDEVICE(S3, PCI_CHIP_PROSAVAGE_KM),
PCI_VDEVICE(S3, PCI_CHIP_S3TWISTER_P),
PCI_VDEVICE(S3, PCI_CHIP_S3TWISTER_K),
PCI_VDEVICE(S3, PCI_CHIP_PROSAVAGE_DDR),
PCI_VDEVICE(S3, PCI_CHIP_PROSAVAGE_DDRK),
__set_bit(S3, next);
__set_bit(S3, next);
case S3:
__set_bit(S3, next);
static const u32 S3[64] = {
L ^= S3[0xff & A]; \
{ PCI_VDEVICE(S3, 0xca00) },