BB
#define BBA BB + 1
{"crnor", XL(19,33), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
{"crandc", XL(19,129), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
{"crxor", XL(19,193), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
{"crnand", XL(19,225), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
{"crand", XL(19,257), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
{"creqv", XL(19,289), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
{"crorc", XL(19,417), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
{"cror", XL(19,449), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
{"e_crandc", XL(31,129), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
{"e_crnand", XL(31,225), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
{"e_crnor", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
{"e_crxor", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
{"e_crand", XL(31,257), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
{"e_creqv", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
{"e_crorc", XL(31,417), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
{"e_cror", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, BB) |
FIELD_GET(BB, val), \
TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2),
TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4),
TEGRA234_AON_GPIO_PORT(BB, 0, 5, 4),
TEGRA241_AON_GPIO_PORT(BB, 0, 0, 4),
TEGRA264_AON_GPIO_PORT(BB, 0, 1, 2),
CASE_BTC_REGTYPE_STR(BB);