SAR
__raw_writel(chan->sar, (dma_base_addr(chan->chan) + SAR));
channel_readl(dwc, SAR),
channel_writel(dwc, SAR, lli_read(desc, sar));
DW_REG(SAR); /* Source Address Register */
channel_writeq(idma64c, SAR, 0);
off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
sh_dmae_writel(sh_chan, hw->sar, SAR);
u32 sar_buf = sh_dmae_readl(sh_chan, SAR);
channel64_readq(dc, SAR),
channel32_readl(dc, SAR),
channel_writeq(dc, SAR, 0);
channel_writel(dc, SAR, 0);
(u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR);
(u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR,
d->CHAR, d->SAR, d->DAR, d->CNTR);
d->CHAR, d->SAR, d->DAR, d->CNTR,
desc->hwdesc.SAR = src + offset;
desc->hwdesc32.SAR = src + offset;
desc->hwdesc.SAR = mem;
desc->hwdesc.SAR = ds->rx_reg;
desc->hwdesc32.SAR = mem;
desc->hwdesc32.SAR = ds->rx_reg;
u64 SAR;
u32 SAR;
u64 SAR; /* Source Address Register */
u32 SAR;
rcar_i2c_write(priv, ICSIER, SAR);
if (ssr_filtered & SAR) {
rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR);
rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR);
rcar_i2c_write(priv, ICSSR, ~(SAR | SSR) & 0xff);
rcar_i2c_write(priv, ICSIER, SAR);