arch/arm/include/asm/cachetype.h

100

writel(cache_selector, BASEADDR_V7M_SCB + V7M_SCB_CTR);

arch/arm/include/asm/cachetype.h

105

return readl(BASEADDR_V7M_SCB + V7M_SCB_CCSIDR);

arch/arm/include/asm/cachetype.h

110

return readl(BASEADDR_V7M_SCB + V7M_SCB_CLIDR);

arch/arm/include/asm/cputype.h

159

return readl(BASEADDR_V7M_SCB + offset);

arch/arm/include/asm/cputype.h

203

return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);

arch/arm/include/asm/cputype.h

208

return readl(BASEADDR_V7M_SCB + V7M_SCB_CTR);

arch/arm/include/asm/cputype.h

213

return readl(BASEADDR_V7M_SCB + MPU_TYPE);

arch/arm/kernel/v7m.c

14

BASEADDR_V7M_SCB + V7M_SCB_AIRCR);

arch/arm/mm/pmsa-v7.c

105

writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv7_RNR);

arch/arm/mm/pmsa-v7.c

113

u32 rsr = readl_relaxed(BASEADDR_V7M_SCB + PMSAv7_RASR) & GENMASK(15, 0);

arch/arm/mm/pmsa-v7.c

115

writel_relaxed((v << 16) | rsr, BASEADDR_V7M_SCB + PMSAv7_RASR);

arch/arm/mm/pmsa-v7.c

121

u32 racr = readl_relaxed(BASEADDR_V7M_SCB + PMSAv7_RASR) & GENMASK(31, 16);

arch/arm/mm/pmsa-v7.c

123

writel_relaxed(v | racr, BASEADDR_V7M_SCB + PMSAv7_RASR);

arch/arm/mm/pmsa-v7.c

129

writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv7_RBAR);

arch/arm/mm/pmsa-v7.c

134

return readl_relaxed(BASEADDR_V7M_SCB + PMSAv7_RBAR);

arch/arm/mm/pmsa-v8.c

53

return readl_relaxed(BASEADDR_V7M_SCB + PMSAv8_RLAR);

arch/arm/mm/pmsa-v8.c

58

return readl_relaxed(BASEADDR_V7M_SCB + PMSAv8_RBAR);

arch/arm/mm/pmsa-v8.c

63

writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv8_RNR);

arch/arm/mm/pmsa-v8.c

68

writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv8_RBAR);

arch/arm/mm/pmsa-v8.c

73

writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv8_RLAR);

drivers/irqchip/irq-nvic.c

42

unsigned long icsr = readl_relaxed(BASEADDR_V7M_SCB + V7M_SCB_ICSR);