R_P0_TRSW
rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_ANT_TRAIN_EN,
rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_TX_ANT_SEL,
rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_BT_FORCE_ANTIDX_EN,
rtw89_phy_write32_mask(rtwdev, R_P0_TRSW,
rtw89_phy_write32_set(rtwdev, R_P0_TRSW, B_P0_TRSW_A);
rtw89_phy_write32_clr(rtwdev, R_P0_TRSW, B_P0_TRSW_X);
rtw89_phy_write32_clr(rtwdev, R_P0_TRSW, B_P0_TRSW_SO_A2);