S5H1411_I2C_QAM_ADDR
{ S5H1411_I2C_QAM_ADDR, 0xf3, 0x0000, },
{ S5H1411_I2C_QAM_ADDR, 0xf3, 0x0001, },
{ S5H1411_I2C_QAM_ADDR, 0x08, 0x0600, },
{ S5H1411_I2C_QAM_ADDR, 0x18, 0x4201, },
{ S5H1411_I2C_QAM_ADDR, 0x1e, 0x6476, },
{ S5H1411_I2C_QAM_ADDR, 0x21, 0x0830, },
{ S5H1411_I2C_QAM_ADDR, 0x0c, 0x5679, },
{ S5H1411_I2C_QAM_ADDR, 0x0d, 0x579b, },
{ S5H1411_I2C_QAM_ADDR, 0x24, 0x0102, },
{ S5H1411_I2C_QAM_ADDR, 0x31, 0x7488, },
{ S5H1411_I2C_QAM_ADDR, 0x32, 0x0a08, },
{ S5H1411_I2C_QAM_ADDR, 0x3d, 0x8689, },
{ S5H1411_I2C_QAM_ADDR, 0x49, 0x0048, },
{ S5H1411_I2C_QAM_ADDR, 0x57, 0x2012, },
{ S5H1411_I2C_QAM_ADDR, 0x5d, 0x7676, },
{ S5H1411_I2C_QAM_ADDR, 0x04, 0x0400, },
{ S5H1411_I2C_QAM_ADDR, 0x58, 0x00c0, },
{ S5H1411_I2C_QAM_ADDR, 0x5b, 0x0100, },
s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x10d9);
s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x1225);
s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x14bd);
s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x1be4);
s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x16, 0x1101);