S0
S0(r1, r2, r0, r4, r3); store_and_load_keys(r0, r2, r4, r1, 8, 4);
S0(r0, r1, r3, r4, r2); store_and_load_keys(r3, r1, r4, r0, -24, -28);
S0(r3, r0, r2, r4, r1); store_and_load_keys(r2, r0, r4, r3, -6, -10);
S0(r2, r3, r1, r4, r0); store_and_load_keys(r1, r3, r4, r2, 12, 8);
S0(r0, r1, r2, r3, r4); LK(r2, r1, r3, r0, r4, 1);
S0(r2, r0, r4, r3, r1); LK(r4, r0, r3, r2, r1, 9);
S0(r4, r2, r1, r3, r0); LK(r1, r2, r3, r4, r0, 17);
S0(r1, r4, r0, r3, r2); LK(r0, r4, r3, r1, r2, 25);
[S0] = vsc9959_vcap_regmap,
[S0] = "s0",
.target = S0,
[S0] = "s0",
[S0] = vsc9953_vcap_regmap,
[S0] = "s0",
.target = S0,
{ S0, "s0" },
[S0] = vsc7514_vcap_regmap,
.target = S0,
__set_bit(S0, mon->states);
case S0:
__set_bit(S0, next);
__set_bit(S0, mon->states);
case S0:
__set_bit(S0, next);
__set_bit(S0, next);
__set_bit(S0, next);
__set_bit(S0, next);
__set_bit(S0, next);