R_TXFIR0
rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3b13ff);
rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3d23ff);
#define __DFIR_CFG_ADDR(i) (R_TXFIR0 + ((i) << 2))
rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01,
rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01,
#define __DFIR_CFG_ADDR(i) (R_TXFIR0 + ((i) << 2))
rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3b13ff);
rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3d23ff);