R_P1_TXPW_RSTB
rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1);
rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3);
rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
static const u32 ctrl_bbrst[2] = {R_P0_TXPW_RSTB, R_P1_TXPW_RSTB};
rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1);
rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3);
rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB,
rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB,
rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1);
rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3);
rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1);
rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3);
rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1);
rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3);
rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB,
rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB,
rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB,
rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB,