BAR_0
.rg.bar = BAR_0,
fw_status = vkread32(vk, BAR_0, VK_BAR_FWSTS);
fw_status = vkread32(vk, BAR_0, VK_BAR_FWSTS);
vkwrite32(vk, db_val, BAR_0, VK_BAR0_RESET_DB_BASE);
boot_status = vkread32(vk, BAR_0, BAR_BOOT_STATUS);
value = vkread32(vk, BAR_0, BAR_CODEPUSH_SBL);
vkwrite32(vk, value, BAR_0, BAR_CODEPUSH_SBL);
vkwrite32(vk, VK_BAR0_RESET_RAMPDUMP, BAR_0, VK_BAR_FWSTS);
vkwrite32(vk, VK_FWSTS_RESET_MBOX_DB, BAR_0, VK_BAR_FWSTS);
vkwrite32(vk, 0, BAR_0, bar0_reg_clr_list[i]);
boot_status = vkread32(vk, BAR_0, BAR_BOOT_STATUS);
reg = vkread32(vk, BAR_0, BAR_BOOT_STATUS);
vkwrite32(vk, reg, BAR_0, BAR_BOOT_STATUS);
reg = vkread32(vk, BAR_0, BAR_INTF_VER);
reg = vkread32(vk, BAR_0, BAR_CARD_ERR_MEM);
reg = vkread32(vk, BAR_0, BAR_CARD_ERR_MEM);
reg = vkread32(vk, BAR_0, BAR_CARD_ERR_LOG);
boot_status = vkread32(vk, BAR_0, BAR_BOOT_STATUS);
offset = vkread32(vk, BAR_0, BAR_CARD_STATIC_INFO);
value = vkread32(vk, BAR_0, BAR_BOOTSRC_SELECT);
vkwrite32(vk, value, BAR_0, BAR_BOOTSRC_SELECT);
vkwrite32(vk, CODEPUSH_BOOTSTART, BAR_0, offset_codepush);
ret = bcm_vk_wait(vk, BAR_0, BAR_BOOT_STATUS, SRAM_OPEN,
ret = bcm_vk_wait(vk, BAR_0, BAR_BOOT_STATUS, DDR_OPEN,
vkwrite32(vk, codepush, BAR_0, offset_codepush);
ret = bcm_vk_wait(vk, BAR_0, BAR_BOOT_STATUS,
boot_status = vkread32(vk, BAR_0, BAR_BOOT_STATUS);
reg = vkread32(vk, BAR_0, BAR_BOOT1_STDALONE_PROGRESS);
ret = bcm_vk_wait(vk, BAR_0, BAR_BOOT_STATUS,
ret = bcm_vk_wait(vk, BAR_0, offset_codepush,
vkwrite32(vk, codepush, BAR_0, offset_codepush);
ret = bcm_vk_wait(vk, BAR_0, VK_BAR_FWSTS,
is_stdalone = vkread32(vk, BAR_0, BAR_BOOT_STATUS) &
boot_status = vkread32(vk, BAR_0, BAR_BOOT_STATUS);
fw_status = vkread32(vk, BAR_0, VK_BAR_FWSTS);
rev = MAJOR_SOC_REV(vkread32(vk, BAR_0, BAR_CHIP_ID));
uptime_s = vkread32(vk, BAR_0, BAR_OS_UPTIME);
vkwrite32(vk, db_val, BAR_0, qinfo->q_db_offset);
card_status = vkread32(vk, BAR_0, BAR_CARD_STATUS);
vkwrite32(vk, db_val, BAR_0,
card_status = vkread32(vk, BAR_0, BAR_CARD_STATUS);
err = pcim_iomap_regions(pdev, BIT(BAR_0), pci_name(pdev));
dw->rg_region.vaddr = pcim_iomap_table(pdev)[BAR_0];
dw->rg_region.paddr = pdev->resource[BAR_0].start;
if (is_am654_pci_dev(pdev) && bar == BAR_0)
enum pci_barno test_reg_bar = BAR_0;
.test_reg_bar = BAR_0,
adapter->hw.hw_addr = pci_iomap(pdev, BAR_0, 0);
tp->regs = pci_ioremap_bar(pdev, BAR_0);
hw->hw_addr = pci_ioremap_bar(pdev, BAR_0);
[BAR_CONFIG] = BAR_0,
[BAR_CONFIG] = BAR_0,
[BAR_PEER_SPAD] = BAR_0,
[BAR_CONFIG] = BAR_0,
[BAR_PEER_SPAD] = BAR_0,
if (pci_epc_get_first_free_bar(epc_features) != BAR_0) {
epf->bar[BAR_0].flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
if (epc_features->bar[BAR_0].type == BAR_FIXED) {
if (reg_size > epc_features->bar[BAR_0].fixed_size) {
epc_features->bar[BAR_0].fixed_size,
reg_bar_size = epc_features->bar[BAR_0].fixed_size;
nvme_epf->reg_bar = pci_epf_alloc_space(epf, reg_bar_size, BAR_0,
pci_epf_free_space(epf, nvme_epf->reg_bar, BAR_0, PRIMARY_INTERFACE);
&epf->bar[BAR_0]);
epf->msix_interrupts, BAR_0,
&epf->bar[BAR_0]);
bar = (enum cdns_pcie_rp_bar)BAR_0;
for (bar = BAR_0; bar <= BAR_5; bar++)
.bar[BAR_0] = { .type = BAR_RESERVED, },
.bar[BAR_0] = { .type = BAR_RESIZABLE, },
.bar[BAR_0] = { .type = BAR_RESIZABLE, },
.bar[BAR_0] = { .only_64bit = true, },
.bar[BAR_0] = { .only_64bit = true, },
for (bar = BAR_0; bar <= BAR_5; bar++)
.bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M,
for (bar = BAR_0; bar <= BAR_5; bar++)
.bar[BAR_0] = { .only_64bit = true, },
.bar[BAR_0] = { .only_64bit = true, },
.bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = 128,
.bar_num = BAR_0,
.bar_num = BAR_0,
.bar_num = BAR_0,
barno = BAR_0;
for (bar = BAR_0; bar < PCI_STD_NUM_BARS; bar++) {
enum pci_barno test_reg_bar = BAR_0;
PCI_EPF_TEST_BAR_SIZE_R(bar0_size, BAR_0)
PCI_EPF_TEST_BAR_SIZE_W(bar0_size, BAR_0)
for (bar = BAR_0; bar < PCI_STD_NUM_BARS; bar++)
if (bar < BAR_0)
if (bar < BAR_0)
barno = BAR_0;
return pci_epc_get_next_free_bar(epc_features, BAR_0);
return BAR_0;
if (!(pci_resource_flags(pdev, BAR_0) & IORESOURCE_MEM) ||
pci_resource_flags(pdev, BAR_0) & IORESOURCE_MEM_64 ||
pci_resource_len(pdev, BAR_0) < TSI721_REG_SPACE_SIZE) {
priv->regs = pci_ioremap_bar(pdev, BAR_0);