drivers/gpio/gpio-pca953x.c

1155

bitmap_set_value8(val, 0x02, i * BANK_SZ);

drivers/gpio/gpio-pca953x.c

191

#define MAX_LINE (MAX_BANK * BANK_SZ)

drivers/gpio/gpio-pca953x.c

193

#define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ)

drivers/gpio/gpio-pca953x.c

253

return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);

drivers/gpio/gpio-pca953x.c

263

unsigned int bit_pos_in_bank = offset % BANK_SZ;

drivers/gpio/gpio-pca953x.c

264

int msb = BANK_SZ - 1;

drivers/gpio/gpio-pca953x.c

522

u8 regaddr = pinctrl | addr | (off / BANK_SZ);

drivers/gpio/gpio-pca953x.c

559

return pinctrl + addr + (off / BANK_SZ);

drivers/gpio/gpio-pca953x.c

569

return reg_base + (offset / BANK_SZ);

drivers/gpio/gpio-pca953x.c

579

value[i] = bitmap_get_value8(val, i * BANK_SZ);

drivers/gpio/gpio-pca953x.c

603

bitmap_set_value8(val, value[i], i * BANK_SZ);

drivers/gpio/gpio-pca953x.c

743

u8 bit = BIT(offset % BANK_SZ);

drivers/pinctrl/pinctrl-cy8c95x0.c

1425

chip->nport = DIV_ROUND_UP(CY8C95X0_PIN_TO_OFFSET(chip->tpin), BANK_SZ);

drivers/pinctrl/pinctrl-cy8c95x0.c

320

return CY8C95X0_PIN_TO_OFFSET(pin) / BANK_SZ;

drivers/pinctrl/pinctrl-cy8c95x0.c

326

return BIT(CY8C95X0_PIN_TO_OFFSET(pin) % BANK_SZ);

drivers/pinctrl/pinctrl-cy8c95x0.c

630

for_each_set_clump8(offset, bits, tmask, chip->nport * BANK_SZ) {

drivers/pinctrl/pinctrl-cy8c95x0.c

658

for_each_set_clump8(offset, bits, tmask, chip->nport * BANK_SZ) {

drivers/pinctrl/pinctrl-cy8c95x0.c

68

#define MAX_LINE (MAX_BANK * BANK_SZ)