R_BE_HAXI_INIT_CFG1
val = rtw89_read32(rtwdev, R_BE_HAXI_INIT_CFG1);
rtw89_write32(rtwdev, R_BE_HAXI_INIT_CFG1, val);
val = rtw89_read32(rtwdev, R_BE_HAXI_INIT_CFG1);
rtw89_write32(rtwdev, R_BE_HAXI_INIT_CFG1, val);
val32_init1 = rtw89_read32(rtwdev, R_BE_HAXI_INIT_CFG1);
rtw89_write32(rtwdev, R_BE_HAXI_INIT_CFG1, val32_init1);
rtw89_write32_set(rtwdev, R_BE_HAXI_INIT_CFG1, B_BE_SET_BDRAM_BOUND);
50, 500000, false, rtwdev, R_BE_HAXI_INIT_CFG1);
.init_cfg_reg = R_BE_HAXI_INIT_CFG1,
.dma_io_stop = {R_BE_HAXI_INIT_CFG1, B_BE_STOP_AXI_MST},