BANK_0
ret = nct7904_read_reg16(data, BANK_0, FANIN_CTRL0_REG);
ret = nct7904_read_reg16(data, BANK_0, VT_ADC_CTRL0_REG);
ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL2_REG);
ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL0_REG);
ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL2_REG);
ret = nct7904_read_reg(data, BANK_0, VT_ADC_MD_REG);
ret = nct7904_read_reg(data, BANK_0, DTS_T_CTRL0_REG);
ret = nct7904_read_reg(data, BANK_0, DTS_T_CTRL1_REG);
ret = nct7904_read_reg(data, BANK_0, SMI_STS1_REG + i);
ret = nct7904_read_reg16(data, BANK_0,
ret = nct7904_read_reg(data, BANK_0,
ret = nct7904_read_reg16(data, BANK_0,
ret = nct7904_read_reg(data, BANK_0,
ret = nct7904_read_reg16(data, BANK_0, LTD_HV_REG);
ret = nct7904_read_reg16(data, BANK_0,
ret = nct7904_read_reg16(data, BANK_0,
ret = nct7904_read_reg(data, BANK_0,
ret = nct7904_read_reg(data, BANK_0,
ret = nct7904_read_reg(data, BANK_0,
ret = nct7904_read_reg(data, BANK_0,
return nct7904_write_reg(data, BANK_0, WDT_LOCK_REG, WDT_SOFT_EN);
return nct7904_write_reg(data, BANK_0, WDT_LOCK_REG, WDT_SOFT_DIS);
return nct7904_write_reg(data, BANK_0, WDT_TIMER_REG,
ret = nct7904_write_reg(data, BANK_0, WDT_LOCK_REG, WDT_SOFT_DIS);
ret = nct7904_write_reg(data, BANK_0, WDT_TIMER_REG, wdt->timeout / 60);
return nct7904_write_reg(data, BANK_0, WDT_LOCK_REG, WDT_SOFT_EN);
ret = nct7904_read_reg(data, BANK_0, WDT_TIMER_REG);
outb(BANK_0, ioaddr + CONFIG_1);
outb(BANK_0, ioaddr + CONFIG_1);