R_BE_FEN_RST_ENABLE
rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE, set);
rtw89_write32_clr(rtwdev, R_BE_FEN_RST_ENABLE, set);
rtw89_write32_clr(rtwdev, R_BE_FEN_RST_ENABLE,
rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE,
rtw89_write32_clr(rtwdev, R_BE_FEN_RST_ENABLE,
rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE,
rtw89_write32_clr(rtwdev, R_BE_FEN_RST_ENABLE,
rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE,
rtw89_write32_clr(rtwdev, R_BE_FEN_RST_ENABLE,
rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE,
val = rtw89_read32(rtwdev, R_BE_FEN_RST_ENABLE);
rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, glbrst_mask[phy_idx], 0x0);
rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, bbrst_mask[phy_idx], 0x0);
rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, glbrst_mask[phy_idx], 0x1);
rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, mcu_bootrdy_mask[phy_idx], rdy);
rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE, mcu_bootrdy_mask[phy_idx]);
rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE, bbrst_mask[phy_idx]);
rtw89_write8_set(rtwdev, R_BE_FEN_RST_ENABLE,
rtw89_write8_clr(rtwdev, R_BE_FEN_RST_ENABLE,
rtw89_write32_clr(rtwdev, R_BE_FEN_RST_ENABLE, B_BE_R_SYM_ISO_ADDA_P02PP |
rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE, B_BE_FEN_BB_IP_RSTN |
rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE, B_BE_R_SYM_ISO_ADDA_P02PP |
rtw89_write8_clr(rtwdev, R_BE_FEN_RST_ENABLE, B_BE_FEN_BB_IP_RSTN |