R_AX_HAXI_INIT_CFG1
val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1);
rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val);
rtw89_write32_mask(rtwdev, R_AX_HAXI_INIT_CFG1, B_AX_HAXI_MAX_TXDMA_MASK, tx_burst);
rtw89_write32_mask(rtwdev, R_AX_HAXI_INIT_CFG1, B_AX_HAXI_MAX_RXDMA_MASK, rx_burst);
rtw89_write32_mask(rtwdev, R_AX_HAXI_INIT_CFG1, B_AX_WD_ITVL_IDLE_V1_MASK,
rtw89_write32_mask(rtwdev, R_AX_HAXI_INIT_CFG1, B_AX_WD_ITVL_ACT_V1_MASK,
.init_cfg_reg = R_AX_HAXI_INIT_CFG1,
.dma_io_stop = {R_AX_HAXI_INIT_CFG1, B_AX_STOP_AXI_MST},