RV1126_CLKSEL_CON
RV1126_CLKSEL_CON(64), 0, 5, DFLAGS,
RV1126_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS |
RV1126_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS,
.core_reg[0] = RV1126_CLKSEL_CON(0),
RV1126_CLKSEL_CON(10), 10, 2, MFLAGS);
RV1126_CLKSEL_CON(12), 10, 2, MFLAGS);
RV1126_CLKSEL_CON(14), 10, 2, MFLAGS);
RV1126_CLKSEL_CON(16), 10, 2, MFLAGS);
RV1126_CLKSEL_CON(18), 10, 2, MFLAGS);
RV1126_CLKSEL_CON(30), 0, 2, MFLAGS);
RV1126_CLKSEL_CON(30), 2, 2, MFLAGS);
RV1126_CLKSEL_CON(31), 8, 2, MFLAGS);
RV1126_CLKSEL_CON(33), 8, 2, MFLAGS);
RV1126_CLKSEL_CON(36), 8, 2, MFLAGS);
RV1126_CLKSEL_CON(47), 10, 2, MFLAGS);
RV1126_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
RV1126_CLKSEL_CON(0), 8, 5, DFLAGS,
RV1126_CLKSEL_CON(2), 6, 2, MFLAGS, 0, 5, DFLAGS,
RV1126_CLKSEL_CON(2), 15, 1, MFLAGS, 8, 5, DFLAGS,
RV1126_CLKSEL_CON(3), 7, 1, MFLAGS, 0, 5, DFLAGS,
RV1126_CLKSEL_CON(3), 15, 1, MFLAGS, 8, 5, DFLAGS,
RV1126_CLKSEL_CON(10), 8, 2, MFLAGS, 0, 7, DFLAGS,
RV1126_CLKSEL_CON(11), 0,
RV1126_CLKSEL_CON(12), 8, 2, MFLAGS, 0, 7, DFLAGS,
RV1126_CLKSEL_CON(13), 0,
RV1126_CLKSEL_CON(14), 8, 2, MFLAGS, 0, 7, DFLAGS,
RV1126_CLKSEL_CON(15), 0,
RV1126_CLKSEL_CON(16), 8, 2, MFLAGS, 0, 7,
RV1126_CLKSEL_CON(17), 0,
RV1126_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7,
RV1126_CLKSEL_CON(19), 0,
RV1126_CLKSEL_CON(5), 0, 7, DFLAGS,
RV1126_CLKSEL_CON(5), 8, 7, DFLAGS,
RV1126_CLKSEL_CON(6), 0, 7, DFLAGS,
RV1126_CLKSEL_CON(6), 8, 7, DFLAGS,
RV1126_CLKSEL_CON(8), 7, 1, MFLAGS, 0, 7, DFLAGS,
RV1126_CLKSEL_CON(9), 15, 1, MFLAGS, 8, 7, DFLAGS,
RV1126_CLKSEL_CON(21), 15, 1, MFLAGS,
RV1126_CLKSEL_CON(22), 15, 1, MFLAGS,
RV1126_CLKSEL_CON(23), 15, 1, MFLAGS,
RV1126_CLKSEL_CON(24), 15, 1, MFLAGS,
RV1126_CLKSEL_CON(20), 0, 11, DFLAGS,
RV1126_CLKSEL_CON(25), 15, 1, MFLAGS, 8, 7, DFLAGS,
RV1126_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 7, DFLAGS,
RV1126_CLKSEL_CON(71), 0, 11, DFLAGS,
RV1126_CLKSEL_CON(70), 0, 11, DFLAGS,
RV1126_CLKSEL_CON(26), 0, 5, DFLAGS,
RV1126_CLKSEL_CON(27), 7, 1, MFLAGS, 0, 7, DFLAGS,
RV1126_CLKSEL_CON(28), 0,
RV1126_CLKSEL_CON(27), 15, 1, MFLAGS, 8, 7, DFLAGS,
RV1126_CLKSEL_CON(29), 0,
RV1126_CLKSEL_CON(30), 6, 1, MFLAGS,
RV1126_CLKSEL_CON(30), 8, 1, MFLAGS,
RV1126_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 7, DFLAGS,
RV1126_CLKSEL_CON(32), 0,
RV1126_CLKSEL_CON(31), 12, 1, MFLAGS,
RV1126_CLKSEL_CON(33), 7, 1, MFLAGS, 0, 7, DFLAGS,
RV1126_CLKSEL_CON(34), 0,
RV1126_CLKSEL_CON(33), 10, 1, MFLAGS,
RV1126_CLKSEL_CON(35), 8, 2, MFLAGS, 0, 7, DFLAGS,
RV1126_CLKSEL_CON(36), 7, 1, MFLAGS, 0, 7, DFLAGS,
RV1126_CLKSEL_CON(37), 0,
RV1126_CLKSEL_CON(72), 8, 1, MFLAGS, 0, 7, DFLAGS,
RV1126_CLKSEL_CON(45), 7, 1, MFLAGS, 0, 5, DFLAGS,
RV1126_CLKSEL_CON(45), 8, 5, DFLAGS,
RV1126_CLKSEL_CON(46), 8, 5, DFLAGS,
RV1126_CLKSEL_CON(46), 7, 1, MFLAGS, 0, 5, DFLAGS,
RV1126_CLKSEL_CON(47), 8, 1, MFLAGS, 0, 8, DFLAGS,
CLK_SET_RATE_PARENT, RV1126_CLKSEL_CON(48), 0,
RV1126_CLKSEL_CON(54), 7, 1, MFLAGS, 0, 5, DFLAGS,
RV1126_CLKSEL_CON(53), 7, 1, MFLAGS, 0, 5, DFLAGS,
RV1126_CLKSEL_CON(53), 8, 5, DFLAGS,
RV1126_CLKSEL_CON(55), 14, 2, MFLAGS, 0, 8,
RV1126_CLKSEL_CON(56), 14, 2, MFLAGS, 0, 8, DFLAGS,
RV1126_CLKSEL_CON(57), 14, 2, MFLAGS, 0, 8, DFLAGS,
RV1126_CLKSEL_CON(59), 15, 1, MFLAGS, 0, 8, DFLAGS,
RV1126_CLKSEL_CON(58), 15, 1, MFLAGS, 0, 8, DFLAGS,
RV1126_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 5, DFLAGS,
RV1126_CLKSEL_CON(63), 8, 5, DFLAGS,
RV1126_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 5, DFLAGS,
.reg = RV1126_CLKSEL_CON(1), \
RV1126_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 5, DFLAGS,
RV1126_CLKSEL_CON(1), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,