arch/riscv/include/asm/insn.h

212

#define RVG_MASK_JALR (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)

arch/riscv/include/asm/insn.h

219

#define RVG_MASK_BEQ (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)

arch/riscv/include/asm/insn.h

220

#define RVG_MASK_BNE (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)

arch/riscv/include/asm/insn.h

221

#define RVG_MASK_BLT (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)

arch/riscv/include/asm/insn.h

222

#define RVG_MASK_BGE (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)

arch/riscv/include/asm/insn.h

223

#define RVG_MASK_BLTU (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)

arch/riscv/include/asm/insn.h

224

#define RVG_MASK_BGEU (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)

arch/riscv/include/asm/insn.h

460

RV_INSN_FUNCT3_MASK >> RV_INSN_FUNCT3_OPOFF)); })