arch/riscv/include/asm/insn.h

409

#define GET_RS2S(insn, regs) (*REG_PTR(RVC_RS2S(insn), 0, regs))

arch/riscv/kernel/traps_misaligned.c

126

#define GET_F64_RS2S(insn, regs) (get_f64_rs(RVC_RS2S(insn), 0, regs))

arch/riscv/kernel/traps_misaligned.c

130

#define GET_F32_RS2S(insn, regs) (get_f32_rs(RVC_RS2S(insn), 0, regs))

arch/riscv/kernel/traps_misaligned.c

268

insn = RVC_RS2S(insn) << SH_RD;

arch/riscv/kernel/traps_misaligned.c

277

insn = RVC_RS2S(insn) << SH_RD;

arch/riscv/kernel/traps_misaligned.c

285

insn = RVC_RS2S(insn) << SH_RD;

arch/riscv/kernel/traps_misaligned.c

293

insn = RVC_RS2S(insn) << SH_RD;

arch/riscv/kernel/traps_misaligned.c

300

insn = RVC_RS2S(insn) << SH_RD;

arch/riscv/kernel/traps_misaligned.c

304

insn = RVC_RS2S(insn) << SH_RD;

arch/riscv/kvm/vcpu_insn.c

435

insn = RVC_RS2S(insn) << SH_RD;

arch/riscv/kvm/vcpu_insn.c

444

insn = RVC_RS2S(insn) << SH_RD;