RTXAGC_A_MCS07_MCS04
if (regaddr == RTXAGC_A_MCS07_MCS04) {
RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
if (regaddr == RTXAGC_A_MCS07_MCS04) {
RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
(regoffset == RTXAGC_A_MCS07_MCS04 ||
regoffset == RTXAGC_A_MCS07_MCS04)
RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
(regoffset == RTXAGC_A_MCS07_MCS04 ||
regoffset == RTXAGC_A_MCS07_MCS04)
else if (regaddr == RTXAGC_A_MCS07_MCS04)
RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
(regoffset == RTXAGC_A_MCS07_MCS04 ||
regoffset == RTXAGC_A_MCS07_MCS04)
rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE0,
rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE1,
rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE2,
rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE3,
case RTXAGC_A_MCS07_MCS04:
if (regaddr == RTXAGC_A_MCS07_MCS04) {
RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
(regoffset == RTXAGC_A_MCS07_MCS04 ||
regoffset == RTXAGC_A_MCS07_MCS04)
rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS07_MCS04,
rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS07_MCS04,
rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS07_MCS04,
rtl8723_phy_set_bb_reg(hw, RTXAGC_A_MCS07_MCS04,
case RTXAGC_A_MCS07_MCS04:
RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04,
rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04,
rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04,
rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04,
RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,