RTS
if ( (grp1 & TXGROUP) && (scc2->wreg[R5] & RTS) )
if ( !(scc->wreg[R5] & RTS) )
if ( !(scc->wreg[R5] & RTS) )
case PARAM_RTS: return CAST((scc->wreg[R5] & RTS)? 1:0);
if((scc->wreg[5] & RTS) && scc->kiss.fulldup == KISS_DUPLEX_HALF)
scc->wreg[R5] |= RTS;
or(scc,R5,RTS|TxENAB); /* set the RTS line and enable TX */
cl(scc,R5,RTS|TxENAB);
scc->wreg[R5] |= RTS;
or(scc,R5,RTS|TxENAB); /* enable tx */
cl(scc,R5,RTS|TxENAB); /* disable tx */
ctrl.RTS = 0;
port->ctrl_ul.RTS = rts;
return (ctrl_ul->RTS ? TIOCM_RTS : 0)
unsigned int RTS:1;
unsigned int RTS:1;
set_bits |= RTS;
clear_bits |= RTS;
write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR);
set_bits |= RTS;
clear_bits |= RTS;
write_zsreg(uap, 5, Tx8 | RTS);
uap->curregs[R5] = Tx8 | RTS;
set_bits |= RTS;
clear_bits |= RTS;
zport_a->regs[5] |= RTS;
zport_a->regs[5] &= ~RTS;