RTL_W32
RTL_W32 (RxConfig, tp->rx_config);
RTL_W32 (TxConfig, rtl8139_tx_config);
RTL_W32 (RxMissed, 0);
RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
RTL_W32 (PARA78, PARA78_default);
RTL_W32 (PARA7c, PARA7c_default);
RTL_W32 (PARA7c, param[(int) tp->twist_row]
RTL_W32 (PARA7c, 0xfb38de03);
RTL_W32 (FIFOTMS, 0x20);
RTL_W32 (PARA78, PARA78_default);
RTL_W32 (PARA7c, PARA7c_default);
RTL_W32 (FIFOTMS, 0x00);
RTL_W32 (TxConfig, TxClearAbt);
RTL_W32 (RxConfig, tp->rx_config);
RTL_W32 (RxConfig, tp->rx_config);
RTL_W32 (RxMissed, 0);
RTL_W32 (RxMissed, 0);
RTL_W32 (RxMissed, 0);
RTL_W32 (RxMissed, 0);
RTL_W32(tp, ERIDR, val);
RTL_W32(tp, ERIAR, cmd);
RTL_W32(tp, ERIAR, cmd);
RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
RTL_W32(tp, GPHY_OCP, reg << 15);
RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
RTL_W32(tp, OCPDR, reg << 15);
RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
RTL_W32(tp, OCPDR, data);
RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
RTL_W32(tp, IntrStatus_8125, bits);
RTL_W32(tp, IntrMask_8125, 0);
RTL_W32(tp, IntrMask_8125, tp->irq_mask);
RTL_W32(tp, RxConfig, rx_config);
RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr));
RTL_W32(tp, CounterAddrLow, cmd);
RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4));
RTL_W32(tp, MAC0, get_unaligned_le32(addr));
RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST |
RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
RTL_W32(tp, TxConfig, val);
RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
RTL_W32(tp, 0x7c, val);
RTL_W32(tp, MAR0 + 4, mc_filter[1]);
RTL_W32(tp, MAR0 + 0, mc_filter[0]);
RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
RTL_W32(tp, CSIDR, value);
RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
RTL_W32(tp, RSS_CTRL_8125, 0);
RTL_W32(tp, i, 0);
RTL_W32(tp, i, 0);