arch/arm/mach-footbridge/isa-rtc.c

39

CMOS_WRITE(RTC_REF_CLCK_32KHZ, RTC_REG_A);

arch/arm/mach-footbridge/isa-rtc.c

49

if ((CMOS_READ(RTC_REG_A) & 0x7f) == RTC_REF_CLCK_32KHZ &&

arch/mips/kernel/cevt-ds1287.c

39

CMOS_WRITE(RTC_REF_CLCK_32KHZ | rate, RTC_REG_A);

arch/mips/mti-malta/malta-time.c

78

while (CMOS_READ(RTC_REG_A) & RTC_UIP);

arch/mips/mti-malta/malta-time.c

79

while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));

arch/mips/mti-malta/malta-time.c

85

while (CMOS_READ(RTC_REG_A) & RTC_UIP);

arch/mips/mti-malta/malta-time.c

89

while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));

arch/mips/mti-malta/malta-time.c

95

while (CMOS_READ(RTC_REG_A) & RTC_UIP);

include/linux/mc146818rtc.h

74

#define RTC_FREQ_SELECT RTC_REG_A