arch/alpha/kernel/time.c

214

sel = RTC_REF_CLCK_32KHZ + 6;

arch/alpha/kernel/time.c

217

sel = RTC_REF_CLCK_32KHZ + __builtin_ffs(32768 / CONFIG_HZ);

arch/arm/mach-footbridge/isa-rtc.c

39

CMOS_WRITE(RTC_REF_CLCK_32KHZ, RTC_REG_A);

arch/arm/mach-footbridge/isa-rtc.c

49

if ((CMOS_READ(RTC_REG_A) & 0x7f) == RTC_REF_CLCK_32KHZ &&

arch/mips/kernel/cevt-ds1287.c

39

CMOS_WRITE(RTC_REF_CLCK_32KHZ | rate, RTC_REG_A);

arch/mips/mti-malta/malta-time.c

185

if ((freq & RTC_DIV_CTL) != RTC_REF_CLCK_32KHZ)

arch/mips/mti-malta/malta-time.c

186

CMOS_WRITE(RTC_REF_CLCK_32KHZ, RTC_FREQ_SELECT);

drivers/rtc/rtc-cmos.c

1055

CMOS_WRITE(RTC_REF_CLCK_32KHZ | 0x06, RTC_FREQ_SELECT);