RT5677_PWR_ANLG2
{RT5677_PWR_ANLG2 , 0x0000},
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
case RT5677_PWR_ANLG2: /* Modified by DSP firmware */
case RT5677_PWR_ANLG2:
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,