arch/arm/boot/dts/st/st-pincfg.h
51
#define SE_NICLK_IO (RT)
arch/arm/boot/dts/st/st-pincfg.h
56
#define SE_ICLK_IO (RT | INVERTCLK)
arch/arm/boot/dts/st/st-pincfg.h
61
#define DE_IO (RT | DOUBLE_EDGE)
arch/arm/boot/dts/st/st-pincfg.h
66
#define ICLK (RT | CLKNOTDATA | INVERTCLK)
arch/arm/boot/dts/st/st-pincfg.h
71
#define NICLK (RT | CLKNOTDATA)
arch/mips/kernel/traps.c
564
regs->regs[(opcode & RT) >> 16] = value;
arch/mips/kernel/traps.c
587
reg = (opcode & RT) >> 16;
arch/mips/kernel/traps.c
676
int rt = (opcode & RT) >> 16;
arch/mips/kernel/traps.c
720
#define CSR_FUNC_MASK RT
arch/mips/mm/uasm-micromips.c
101
[insn_sll] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sll32_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
102
[insn_sllv] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sllv32_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
103
[insn_slt] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_slt_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
104
[insn_sltiu] = {M(mm_sltiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
arch/mips/mm/uasm-micromips.c
105
[insn_sltu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sltu_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
106
[insn_sra] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
107
[insn_srav] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srav_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
108
[insn_srl] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srl32_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
109
[insn_srlv] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srlv32_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
110
[insn_rotr] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
111
[insn_subu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_subu32_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
112
[insn_sw] = {M(mm_sw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
arch/mips/mm/uasm-micromips.c
119
[insn_wsbh] = {M(mm_pool32a_op, 0, 0, 0, mm_wsbh_op, mm_pool32axf_op), RT | RS},
arch/mips/mm/uasm-micromips.c
120
[insn_xor] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_xor32_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
121
[insn_xori] = {M(mm_xori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM},
arch/mips/mm/uasm-micromips.c
178
if (ip->fields & RT) {
arch/mips/mm/uasm-micromips.c
43
[insn_addu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
44
[insn_addiu] = {M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
arch/mips/mm/uasm-micromips.c
45
[insn_and] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
46
[insn_andi] = {M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM},
arch/mips/mm/uasm-micromips.c
47
[insn_beq] = {M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
arch/mips/mm/uasm-micromips.c
53
[insn_bne] = {M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM},
arch/mips/mm/uasm-micromips.c
54
[insn_cache] = {M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM},
arch/mips/mm/uasm-micromips.c
55
[insn_cfc1] = {M(mm_pool32f_op, 0, 0, 0, mm_cfc1_op, mm_32f_73_op), RT | RS},
arch/mips/mm/uasm-micromips.c
57
[insn_ctc1] = {M(mm_pool32f_op, 0, 0, 0, mm_ctc1_op, mm_32f_73_op), RT | RS},
arch/mips/mm/uasm-micromips.c
62
[insn_divu] = {M(mm_pool32a_op, 0, 0, 0, mm_divu_op, mm_pool32axf_op), RT | RS},
arch/mips/mm/uasm-micromips.c
74
[insn_ins] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_ins_op), RT | RS | RD | RE},
arch/mips/mm/uasm-micromips.c
75
[insn_ext] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_ext_op), RT | RS | RD | RE},
arch/mips/mm/uasm-micromips.c
78
[insn_jalr] = {M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RT | RS},
arch/mips/mm/uasm-micromips.c
80
[insn_lb] = {M(mm_lb32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
arch/mips/mm/uasm-micromips.c
82
[insn_lh] = {M(mm_lh32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
arch/mips/mm/uasm-micromips.c
83
[insn_ll] = {M(mm_pool32c_op, 0, 0, (mm_ll_func << 1), 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-micromips.c
86
[insn_lw] = {M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
arch/mips/mm/uasm-micromips.c
87
[insn_mfc0] = {M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
90
[insn_mtc0] = {M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
93
[insn_mul] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_mul_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
94
[insn_or] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD},
arch/mips/mm/uasm-micromips.c
95
[insn_ori] = {M(mm_ori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM},
arch/mips/mm/uasm-micromips.c
96
[insn_pref] = {M(mm_pool32c_op, 0, 0, (mm_pref_func << 1), 0, 0), RT | RS | SIMM},
arch/mips/mm/uasm-micromips.c
98
[insn_sc] = {M(mm_pool32c_op, 0, 0, (mm_sc_func << 1), 0, 0), RT | RS | SIMM},
arch/mips/mm/uasm-mips.c
100
[insn_dsll32] = {M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE},
arch/mips/mm/uasm-mips.c
101
[insn_dsllv] = {M(spec_op, 0, 0, 0, 0, dsllv_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
102
[insn_dsra] = {M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE},
arch/mips/mm/uasm-mips.c
103
[insn_dsra32] = {M(spec_op, 0, 0, 0, 0, dsra32_op), RT | RD | RE},
arch/mips/mm/uasm-mips.c
104
[insn_dsrav] = {M(spec_op, 0, 0, 0, 0, dsrav_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
105
[insn_dsrl] = {M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE},
arch/mips/mm/uasm-mips.c
106
[insn_dsrl32] = {M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE},
arch/mips/mm/uasm-mips.c
107
[insn_dsrlv] = {M(spec_op, 0, 0, 0, 0, dsrlv_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
108
[insn_dsubu] = {M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
110
[insn_ext] = {M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE},
arch/mips/mm/uasm-mips.c
111
[insn_ins] = {M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE},
arch/mips/mm/uasm-mips.c
120
[insn_lb] = {M(lb_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
121
[insn_lbu] = {M(lbu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
122
[insn_ld] = {M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
123
[insn_lddir] = {M(lwc2_op, 0, 0, 0, lddir_op, mult_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
125
[insn_ldx] = {M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
126
[insn_lh] = {M(lh_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
127
[insn_lhu] = {M(lhu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
129
[insn_ll] = {M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
130
[insn_lld] = {M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
132
[insn_ll] = {M6(spec3_op, 0, 0, 0, ll6_op), RS | RT | SIMM9},
arch/mips/mm/uasm-mips.c
133
[insn_lld] = {M6(spec3_op, 0, 0, 0, lld6_op), RS | RT | SIMM9},
arch/mips/mm/uasm-mips.c
135
[insn_lui] = {M(lui_op, 0, 0, 0, 0, 0), RT | SIMM},
arch/mips/mm/uasm-mips.c
136
[insn_lw] = {M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
137
[insn_lwu] = {M(lwu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
138
[insn_lwx] = {M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
139
[insn_mfc0] = {M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},
arch/mips/mm/uasm-mips.c
140
[insn_mfhc0] = {M(cop0_op, mfhc0_op, 0, 0, 0, 0), RT | RD | SET},
arch/mips/mm/uasm-mips.c
144
RS | RT | RD},
arch/mips/mm/uasm-mips.c
145
[insn_movn] = {M(spec_op, 0, 0, 0, 0, movn_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
146
[insn_movz] = {M(spec_op, 0, 0, 0, 0, movz_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
147
[insn_mtc0] = {M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
arch/mips/mm/uasm-mips.c
148
[insn_mthc0] = {M(cop0_op, mthc0_op, 0, 0, 0, 0), RT | RD | SET},
arch/mips/mm/uasm-mips.c
152
RS | RT | RD},
arch/mips/mm/uasm-mips.c
154
RS | RT | RD},
arch/mips/mm/uasm-mips.c
156
[insn_mul] = {M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
158
[insn_mul] = {M(spec_op, 0, 0, 0, mult_mul_op, mult_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
160
[insn_multu] = {M(spec_op, 0, 0, 0, 0, multu_op), RS | RT},
arch/mips/mm/uasm-mips.c
161
[insn_nor] = {M(spec_op, 0, 0, 0, 0, nor_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
162
[insn_or] = {M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
163
[insn_ori] = {M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM},
arch/mips/mm/uasm-mips.c
165
[insn_pref] = {M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
167
[insn_pref] = {M6(spec3_op, 0, 0, 0, pref6_op), RS | RT | SIMM9},
arch/mips/mm/uasm-mips.c
170
[insn_rotr] = {M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE},
arch/mips/mm/uasm-mips.c
171
[insn_sb] = {M(sb_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
173
[insn_sc] = {M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
174
[insn_scd] = {M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
176
[insn_sc] = {M6(spec3_op, 0, 0, 0, sc6_op), RS | RT | SIMM9},
arch/mips/mm/uasm-mips.c
177
[insn_scd] = {M6(spec3_op, 0, 0, 0, scd6_op), RS | RT | SIMM9},
arch/mips/mm/uasm-mips.c
179
[insn_sd] = {M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
180
[insn_seleqz] = {M(spec_op, 0, 0, 0, 0, seleqz_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
181
[insn_selnez] = {M(spec_op, 0, 0, 0, 0, selnez_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
182
[insn_sh] = {M(sh_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
183
[insn_sll] = {M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE},
arch/mips/mm/uasm-mips.c
184
[insn_sllv] = {M(spec_op, 0, 0, 0, 0, sllv_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
185
[insn_slt] = {M(spec_op, 0, 0, 0, 0, slt_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
186
[insn_slti] = {M(slti_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
187
[insn_sltiu] = {M(sltiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
188
[insn_sltu] = {M(spec_op, 0, 0, 0, 0, sltu_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
189
[insn_sra] = {M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE},
arch/mips/mm/uasm-mips.c
190
[insn_srav] = {M(spec_op, 0, 0, 0, 0, srav_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
191
[insn_srl] = {M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE},
arch/mips/mm/uasm-mips.c
192
[insn_srlv] = {M(spec_op, 0, 0, 0, 0, srlv_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
193
[insn_subu] = {M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
194
[insn_sw] = {M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
202
[insn_wsbh] = {M(spec3_op, 0, 0, 0, wsbh_op, bshfl_op), RT | RD},
arch/mips/mm/uasm-mips.c
203
[insn_xor] = {M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
204
[insn_xori] = {M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM},
arch/mips/mm/uasm-mips.c
249
if (ip->fields & RT)
arch/mips/mm/uasm-mips.c
51
[insn_addiu] = {M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
52
[insn_addu] = {M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
53
[insn_and] = {M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
54
[insn_andi] = {M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM},
arch/mips/mm/uasm-mips.c
55
[insn_bbit0] = {M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
arch/mips/mm/uasm-mips.c
56
[insn_bbit1] = {M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
arch/mips/mm/uasm-mips.c
57
[insn_beq] = {M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
arch/mips/mm/uasm-mips.c
58
[insn_beql] = {M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
arch/mips/mm/uasm-mips.c
65
[insn_bne] = {M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
arch/mips/mm/uasm-mips.c
68
[insn_cache] = {M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
70
[insn_cache] = {M6(spec3_op, 0, 0, 0, cache6_op), RS | RT | SIMM9},
arch/mips/mm/uasm-mips.c
72
[insn_cfc1] = {M(cop1_op, cfc_op, 0, 0, 0, 0), RT | RD},
arch/mips/mm/uasm-mips.c
74
[insn_ctc1] = {M(cop1_op, ctc_op, 0, 0, 0, 0), RT | RD},
arch/mips/mm/uasm-mips.c
76
[insn_daddiu] = {M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
arch/mips/mm/uasm-mips.c
77
[insn_daddu] = {M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD},
arch/mips/mm/uasm-mips.c
78
[insn_ddivu] = {M(spec_op, 0, 0, 0, 0, ddivu_op), RS | RT},
arch/mips/mm/uasm-mips.c
80
RS | RT | RD},
arch/mips/mm/uasm-mips.c
81
[insn_di] = {M(cop0_op, mfmc0_op, 0, 12, 0, 0), RT},
arch/mips/mm/uasm-mips.c
82
[insn_dins] = {M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE},
arch/mips/mm/uasm-mips.c
83
[insn_dinsm] = {M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE},
arch/mips/mm/uasm-mips.c
84
[insn_dinsu] = {M(spec3_op, 0, 0, 0, 0, dinsu_op), RS | RT | RD | RE},
arch/mips/mm/uasm-mips.c
85
[insn_divu] = {M(spec_op, 0, 0, 0, 0, divu_op), RS | RT},
arch/mips/mm/uasm-mips.c
87
RS | RT | RD},
arch/mips/mm/uasm-mips.c
88
[insn_dmfc0] = {M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
arch/mips/mm/uasm-mips.c
90
RS | RT | RD},
arch/mips/mm/uasm-mips.c
91
[insn_dmtc0] = {M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
arch/mips/mm/uasm-mips.c
92
[insn_dmultu] = {M(spec_op, 0, 0, 0, 0, dmultu_op), RS | RT},
arch/mips/mm/uasm-mips.c
94
RS | RT | RD},
arch/mips/mm/uasm-mips.c
95
[insn_drotr] = {M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE},
arch/mips/mm/uasm-mips.c
96
[insn_drotr32] = {M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE},
arch/mips/mm/uasm-mips.c
97
[insn_dsbh] = {M(spec3_op, 0, 0, 0, dsbh_op, dbshfl_op), RT | RD},
arch/mips/mm/uasm-mips.c
98
[insn_dshd] = {M(spec3_op, 0, 0, 0, dshd_op, dbshfl_op), RT | RD},
arch/mips/mm/uasm-mips.c
99
[insn_dsll] = {M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE},
arch/powerpc/xmon/ppc-opc.c
3100
{"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3101
{"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3107
{"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3109
{"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3141
{"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
arch/powerpc/xmon/ppc-opc.c
3143
{"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
arch/powerpc/xmon/ppc-opc.c
3146
{"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
arch/powerpc/xmon/ppc-opc.c
3176
{"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3178
{"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3179
{"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3180
{"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3181
{"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3182
{"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3196
{"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3197
{"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3206
{"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3207
{"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3208
{"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3209
{"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3219
{"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3221
{"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3222
{"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3223
{"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3232
{"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3233
{"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3234
{"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3235
{"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3236
{"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3237
{"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3247
{"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3248
{"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3255
{"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3256
{"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3257
{"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3258
{"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3292
{"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
arch/powerpc/xmon/ppc-opc.c
3315
{"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
arch/powerpc/xmon/ppc-opc.c
3326
{"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
arch/powerpc/xmon/ppc-opc.c
3328
{"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
arch/powerpc/xmon/ppc-opc.c
3446
{"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3448
{"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3454
{"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3456
{"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3485
{"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3486
{"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3487
{"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3488
{"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3489
{"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3490
{"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3500
{"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3501
{"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3510
{"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3511
{"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3512
{"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3513
{"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3534
{"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3535
{"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3565
{"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3567
{"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3570
{"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3571
{"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3594
{"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3595
{"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3618
{"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3619
{"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3620
{"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3621
{"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3647
{"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3648
{"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3671
{"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3673
{"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3676
{"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3677
{"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3703
{"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3704
{"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3724
{"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3726
{"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3729
{"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3730
{"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3732
{"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
arch/powerpc/xmon/ppc-opc.c
3733
{"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
arch/powerpc/xmon/ppc-opc.c
3753
{"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
arch/powerpc/xmon/ppc-opc.c
3760
{"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
arch/powerpc/xmon/ppc-opc.c
3770
{"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
arch/powerpc/xmon/ppc-opc.c
3786
{"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
arch/powerpc/xmon/ppc-opc.c
3787
{"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3788
{"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3794
{"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
arch/powerpc/xmon/ppc-opc.c
3797
{"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3798
{"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3799
{"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3800
{"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3809
{"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
arch/powerpc/xmon/ppc-opc.c
3810
{"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3811
{"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3818
{"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3819
{"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3820
{"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3821
{"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
3824
{"mulli", OP(7), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3825
{"muli", OP(7), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3827
{"subfic", OP(8), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3828
{"sfi", OP(8), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3830
{"dozi", OP(9), OP_MASK, M601, PPCVLE, {RT, RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3842
{"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3843
{"ai", OP(12), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3844
{"subic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
arch/powerpc/xmon/ppc-opc.c
3846
{"addic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3847
{"ai.", OP(13), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
arch/powerpc/xmon/ppc-opc.c
3848
{"subic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
arch/powerpc/xmon/ppc-opc.c
3850
{"li", OP(14), DRA_MASK, PPCCOM, PPCVLE, {RT, SI}},
arch/powerpc/xmon/ppc-opc.c
3851
{"lil", OP(14), DRA_MASK, PWRCOM, PPCVLE, {RT, SI}},
arch/powerpc/xmon/ppc-opc.c
3852
{"addi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SI}},
arch/powerpc/xmon/ppc-opc.c
3853
{"cal", OP(14), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
arch/powerpc/xmon/ppc-opc.c
3854
{"subi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSI}},
arch/powerpc/xmon/ppc-opc.c
3855
{"la", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
arch/powerpc/xmon/ppc-opc.c
3857
{"lis", OP(15), DRA_MASK, PPCCOM, PPCVLE, {RT, SISIGNOPT}},
arch/powerpc/xmon/ppc-opc.c
3858
{"liu", OP(15), DRA_MASK, PWRCOM, PPCVLE, {RT, SISIGNOPT}},
arch/powerpc/xmon/ppc-opc.c
3859
{"addis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
arch/powerpc/xmon/ppc-opc.c
3860
{"cau", OP(15), OP_MASK, PWRCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
arch/powerpc/xmon/ppc-opc.c
3861
{"subis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSISIGNOPT}},
arch/powerpc/xmon/ppc-opc.c
4148
{"addpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, DXD}},
arch/powerpc/xmon/ppc-opc.c
4149
{"subpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, NDXD}},
arch/powerpc/xmon/ppc-opc.c
4698
{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4699
{"sf", XO(31,8,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4700
{"subc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
arch/powerpc/xmon/ppc-opc.c
4701
{"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4702
{"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4703
{"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
arch/powerpc/xmon/ppc-opc.c
4705
{"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4706
{"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4708
{"addc", XO(31,10,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4709
{"a", XO(31,10,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4710
{"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4711
{"a.", XO(31,10,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4713
{"mulhwu", XO(31,11,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4714
{"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4718
{"isellt", X(31,15), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
arch/powerpc/xmon/ppc-opc.c
4725
{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, COM, 0, {RT, FXM4}},
arch/powerpc/xmon/ppc-opc.c
4726
{"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, 0, {RT, FXM}},
arch/powerpc/xmon/ppc-opc.c
4728
{"lwarx", X(31,20), XEH_MASK, PPC, 0, {RT, RA0, RB, EH}},
arch/powerpc/xmon/ppc-opc.c
4730
{"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}},
arch/powerpc/xmon/ppc-opc.c
4734
{"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
arch/powerpc/xmon/ppc-opc.c
4735
{"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4756
{"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
arch/powerpc/xmon/ppc-opc.c
4761
{"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
arch/powerpc/xmon/ppc-opc.c
4774
{"iselgt", X(31,47), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
arch/powerpc/xmon/ppc-opc.c
4778
{"addg6s", XO(31,74,0,0), XO_MASK, POWER6, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4782
{"iseleq", X(31,79), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
arch/powerpc/xmon/ppc-opc.c
4784
{"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, CRB}},
arch/powerpc/xmon/ppc-opc.c
4786
{"subf", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4787
{"sub", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RB, RA}},
arch/powerpc/xmon/ppc-opc.c
4788
{"subf.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4789
{"sub.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RB, RA}},
arch/powerpc/xmon/ppc-opc.c
4796
{"lbarx", X(31,52), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
arch/powerpc/xmon/ppc-opc.c
4798
{"ldux", X(31,53), X_MASK, PPC64, 0, {RT, RAL, RB}},
arch/powerpc/xmon/ppc-opc.c
4802
{"lwzux", X(31,55), X_MASK, PPCCOM, 0, {RT, RAL, RB}},
arch/powerpc/xmon/ppc-opc.c
4803
{"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4835
{"mulhd", XO(31,73,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4836
{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4838
{"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4839
{"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4846
{"mfmsr", X(31,83), XRARB_MASK, COM, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
4848
{"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}},
arch/powerpc/xmon/ppc-opc.c
4853
{"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}},
arch/powerpc/xmon/ppc-opc.c
4855
{"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
arch/powerpc/xmon/ppc-opc.c
4862
{"neg", XO(31,104,0,0), XORB_MASK, COM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
4863
{"neg.", XO(31,104,0,1), XORB_MASK, COM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
4865
{"mul", XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4866
{"mul.", XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4876
{"lharx", X(31,116), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
arch/powerpc/xmon/ppc-opc.c
4880
{"lbzux", X(31,119), X_MASK, COM, 0, {RT, RAL, RB}},
arch/powerpc/xmon/ppc-opc.c
4891
{"setb", X(31,128), XRB_MASK|(3<<16), POWER9, 0, {RT, BFA}},
arch/powerpc/xmon/ppc-opc.c
4900
{"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4901
{"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4902
{"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4903
{"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4905
{"adde", XO(31,138,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4906
{"ae", XO(31,138,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4907
{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4908
{"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
4923
{"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}},
arch/powerpc/xmon/ppc-opc.c
4924
{"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
arch/powerpc/xmon/ppc-opc.c
4952
{"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},
arch/powerpc/xmon/ppc-opc.c
4962
{"eratre", X(31,179), X_MASK, PPCA2, 0, {RT, RA, WS}},
arch/powerpc/xmon/ppc-opc.c
4984
{"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
4985
{"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
4986
{"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
4987
{"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
4989
{"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
4990
{"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
4991
{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
4992
{"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5003
{"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
arch/powerpc/xmon/ppc-opc.c
5024
{"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5025
{"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5026
{"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5027
{"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5029
{"mulld", XO(31,233,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5030
{"mulld.", XO(31,233,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5032
{"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5033
{"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5034
{"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5035
{"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5037
{"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5038
{"muls", XO(31,235,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5039
{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5040
{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5063
{"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
arch/powerpc/xmon/ppc-opc.c
5075
{"doz", XO(31,264,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5076
{"doz.", XO(31,264,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5078
{"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5080
{"add", XO(31,266,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5081
{"cax", XO(31,266,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5082
{"add.", XO(31,266,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5083
{"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5085
{"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5095
{"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5099
{"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5100
{"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5107
{"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}},
arch/powerpc/xmon/ppc-opc.c
5114
{"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
arch/powerpc/xmon/ppc-opc.c
5123
{"mfbhrbe", X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}},
arch/powerpc/xmon/ppc-opc.c
5132
{"ldmx", X(31,309), X_MASK, POWER9, 0, {RT, RA0, RB}},
arch/powerpc/xmon/ppc-opc.c
5134
{"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
arch/powerpc/xmon/ppc-opc.c
5136
{"lhzux", X(31,311), X_MASK, COM, 0, {RT, RAL, RB}},
arch/powerpc/xmon/ppc-opc.c
5143
{"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
arch/powerpc/xmon/ppc-opc.c
5145
{"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5146
{"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5147
{"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5148
{"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5149
{"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5150
{"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5151
{"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5152
{"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5153
{"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5154
{"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5155
{"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5156
{"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5157
{"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5158
{"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5159
{"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5160
{"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5161
{"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5162
{"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5163
{"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5164
{"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5165
{"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5166
{"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5167
{"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5168
{"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5169
{"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5170
{"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5171
{"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5172
{"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5173
{"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5174
{"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5175
{"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5176
{"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5177
{"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5178
{"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5179
{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}},
arch/powerpc/xmon/ppc-opc.c
5180
{"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, 0, {RT, SPR}},
arch/powerpc/xmon/ppc-opc.c
5184
{"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}},
arch/powerpc/xmon/ppc-opc.c
5186
{"div", XO(31,331,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5187
{"div.", XO(31,331,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5191
{"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}},
arch/powerpc/xmon/ppc-opc.c
5192
{"mftmr", X(31,366), X_MASK, PPCTMR|E6500, 0, {RT, TMR}},
arch/powerpc/xmon/ppc-opc.c
5196
{"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5197
{"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5198
{"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}},
arch/powerpc/xmon/ppc-opc.c
5199
{"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}},
arch/powerpc/xmon/ppc-opc.c
5200
{"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5201
{"mflr", XSPR(31,339, 8), XSPR_MASK, COM, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5202
{"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5203
{"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5204
{"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5205
{"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}},
arch/powerpc/xmon/ppc-opc.c
5206
{"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}},
arch/powerpc/xmon/ppc-opc.c
5207
{"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1, {RT}},
arch/powerpc/xmon/ppc-opc.c
5208
{"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5209
{"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}},
arch/powerpc/xmon/ppc-opc.c
5210
{"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5211
{"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5212
{"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5213
{"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5214
{"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5215
{"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5216
{"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5217
{"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5218
{"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5219
{"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5220
{"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5221
{"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5222
{"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5223
{"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5224
{"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5225
{"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5226
{"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5227
{"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5228
{"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5229
{"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5230
{"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5231
{"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5232
{"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5233
{"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5234
{"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5235
{"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5236
{"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5237
{"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5238
{"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, 0, {RT, SPRG}},
arch/powerpc/xmon/ppc-opc.c
5239
{"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5240
{"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5241
{"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5242
{"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5243
{"mftbu", XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5244
{"mftb", X(31,339), X_MASK, POWER4|BOOKE, 0, {RT, TBR}},
arch/powerpc/xmon/ppc-opc.c
5245
{"mftbl", XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5246
{"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5247
{"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5248
{"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5249
{"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5250
{"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5251
{"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}},
arch/powerpc/xmon/ppc-opc.c
5252
{"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5253
{"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5254
{"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5255
{"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5256
{"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5257
{"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5258
{"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5259
{"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5260
{"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5261
{"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5262
{"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5263
{"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5264
{"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5265
{"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5266
{"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5267
{"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5268
{"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5269
{"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5270
{"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5271
{"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5272
{"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5273
{"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5274
{"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5275
{"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5276
{"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5277
{"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5278
{"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5279
{"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5280
{"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5281
{"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5282
{"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5283
{"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5284
{"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5285
{"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5286
{"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5287
{"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5288
{"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
arch/powerpc/xmon/ppc-opc.c
5289
{"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5290
{"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
arch/powerpc/xmon/ppc-opc.c
5291
{"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5292
{"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5293
{"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
arch/powerpc/xmon/ppc-opc.c
5294
{"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
arch/powerpc/xmon/ppc-opc.c
5295
{"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5296
{"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5297
{"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5298
{"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5299
{"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5300
{"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5301
{"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5302
{"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5303
{"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5304
{"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}},
arch/powerpc/xmon/ppc-opc.c
5305
{"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5306
{"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5307
{"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5308
{"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5309
{"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5310
{"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5311
{"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5312
{"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5313
{"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5314
{"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5315
{"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5316
{"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5317
{"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5318
{"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5319
{"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5320
{"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5321
{"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5322
{"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5323
{"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5324
{"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5325
{"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5326
{"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5327
{"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5328
{"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5329
{"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5330
{"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5331
{"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5332
{"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5333
{"mfppr", XSPR(31,339,896), XSPR_MASK, POWER7, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5334
{"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER7, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5335
{"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5336
{"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5337
{"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5338
{"mficdbtr", XSPR(31,339,927), XSPR_MASK, TITAN, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5339
{"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5340
{"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5341
{"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5342
{"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5343
{"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5344
{"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5345
{"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5346
{"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5347
{"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5348
{"mfmmucr", XSPR(31,339,946), XSPR_MASK, TITAN, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5349
{"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5350
{"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5351
{"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5352
{"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5353
{"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5354
{"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5355
{"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5356
{"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5357
{"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5358
{"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5359
{"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5360
{"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5361
{"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5362
{"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5363
{"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5364
{"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5365
{"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5366
{"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5367
{"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5368
{"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5369
{"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5370
{"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5371
{"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5372
{"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5373
{"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5374
{"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5375
{"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5376
{"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5377
{"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5378
{"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5379
{"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5381
{"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5382
{"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5383
{"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5384
{"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5385
{"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5386
{"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5387
{"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5388
{"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5389
{"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5390
{"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5391
{"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5392
{"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5393
{"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5394
{"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5395
{"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, 0, {RT}},
arch/powerpc/xmon/ppc-opc.c
5396
{"mfspr", X(31,339), X_MASK, COM, 0, {RT, SPR}},
arch/powerpc/xmon/ppc-opc.c
5398
{"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}},
arch/powerpc/xmon/ppc-opc.c
5402
{"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}},
arch/powerpc/xmon/ppc-opc.c
5406
{"abs", XO(31,360,0,0), XORB_MASK, M601, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5407
{"abs.", XO(31,360,0,1), XORB_MASK, M601, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5409
{"divs", XO(31,363,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5410
{"divs.", XO(31,363,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5416
{"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}},
arch/powerpc/xmon/ppc-opc.c
5417
{"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}},
arch/powerpc/xmon/ppc-opc.c
5418
{"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371|POWER4, {RT}},
arch/powerpc/xmon/ppc-opc.c
5420
{"lwaux", X(31,373), X_MASK, PPC64, 0, {RT, RAL, RB}},
arch/powerpc/xmon/ppc-opc.c
5424
{"lhaux", X(31,375), X_MASK, COM, 0, {RT, RAL, RB}},
arch/powerpc/xmon/ppc-opc.c
5436
{"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5437
{"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5438
{"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5439
{"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5468
{"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5469
{"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5470
{"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5471
{"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5481
{"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
arch/powerpc/xmon/ppc-opc.c
5541
{"divdu", XO(31,457,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5542
{"divdu.", XO(31,457,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5544
{"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5545
{"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5725
{"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2|PPC476, {RT, RA0, RB}},
arch/powerpc/xmon/ppc-opc.c
5731
{"nabs", XO(31,488,0,0), XORB_MASK, M601, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5732
{"nabs.", XO(31,488,0,1), XORB_MASK, M601, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5734
{"divd", XO(31,489,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5735
{"divd.", XO(31,489,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5737
{"divw", XO(31,491,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5738
{"divw.", XO(31,491,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5745
{"cli", X(31,502), XRB_MASK, POWER, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5753
{"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5754
{"lbdx", X(31,515), X_MASK, E500MC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5761
{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5762
{"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5763
{"subco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
arch/powerpc/xmon/ppc-opc.c
5764
{"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5765
{"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5766
{"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
arch/powerpc/xmon/ppc-opc.c
5768
{"addco", XO(31,10,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5769
{"ao", XO(31,10,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5770
{"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5771
{"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5775
{"clcs", X(31,531), XRB_MASK, M601, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5777
{"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}},
arch/powerpc/xmon/ppc-opc.c
5779
{"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, RBX}},
arch/powerpc/xmon/ppc-opc.c
5780
{"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5782
{"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
arch/powerpc/xmon/ppc-opc.c
5783
{"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5804
{"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5805
{"lhdx", X(31,547), X_MASK, E500MC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5814
{"subfo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5815
{"subo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RB, RA}},
arch/powerpc/xmon/ppc-opc.c
5816
{"subfo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5817
{"subo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RB, RA}},
arch/powerpc/xmon/ppc-opc.c
5828
{"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5829
{"lwdx", X(31,579), X_MASK, E500MC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5833
{"lwat", X(31,582), X_MASK, POWER9, 0, {RT, RA0, FC}},
arch/powerpc/xmon/ppc-opc.c
5839
{"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}},
arch/powerpc/xmon/ppc-opc.c
5841
{"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, NBI}},
arch/powerpc/xmon/ppc-opc.c
5842
{"lsi", X(31,597), X_MASK, PWRCOM, 0, {RT, RA0, NB}},
arch/powerpc/xmon/ppc-opc.c
5859
{"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5863
{"ldat", X(31,614), X_MASK, POWER9, 0, {RT, RA0, FC}},
arch/powerpc/xmon/ppc-opc.c
5867
{"nego", XO(31,104,1,0), XORB_MASK, COM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5868
{"nego.", XO(31,104,1,1), XORB_MASK, COM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5870
{"mulo", XO(31,107,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5871
{"mulo.", XO(31,107,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5873
{"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5889
{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5890
{"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5891
{"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5892
{"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5894
{"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5895
{"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5896
{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5897
{"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5899
{"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}},
arch/powerpc/xmon/ppc-opc.c
5948
{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5949
{"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5950
{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5951
{"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5953
{"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5954
{"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5955
{"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5956
{"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5971
{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}},
arch/powerpc/xmon/ppc-opc.c
5982
{"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5983
{"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5984
{"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5985
{"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5987
{"mulldo", XO(31,233,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5988
{"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5990
{"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5991
{"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5992
{"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5993
{"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
5995
{"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5996
{"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5997
{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
5998
{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6004
{"darn", X(31,755), XLRAND_MASK, POWER9, 0, {RT, LRAND}},
arch/powerpc/xmon/ppc-opc.c
6022
{"dozo", XO(31,264,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6023
{"dozo.", XO(31,264,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6025
{"addo", XO(31,266,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6026
{"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6027
{"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6028
{"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6030
{"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6031
{"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6040
{"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}},
arch/powerpc/xmon/ppc-opc.c
6042
{"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}},
arch/powerpc/xmon/ppc-opc.c
6066
{"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6070
{"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}},
arch/powerpc/xmon/ppc-opc.c
6088
{"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6089
{"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6099
{"slbmfev", X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
arch/powerpc/xmon/ppc-opc.c
6100
{"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}},
arch/powerpc/xmon/ppc-opc.c
6102
{"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}},
arch/powerpc/xmon/ppc-opc.c
6113
{"abso", XO(31,360,1,0), XORB_MASK, M601, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
6114
{"abso.", XO(31,360,1,1), XORB_MASK, M601, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
6116
{"divso", XO(31,363,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6117
{"divso.", XO(31,363,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6125
{"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}},
arch/powerpc/xmon/ppc-opc.c
6139
{"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6140
{"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6141
{"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6142
{"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6152
{"slbmfee", X(31,915), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
arch/powerpc/xmon/ppc-opc.c
6153
{"slbmfee", X(31,915), XRA_MASK, PPC64, POWER9, {RT, RB}},
arch/powerpc/xmon/ppc-opc.c
6183
{"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6184
{"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6185
{"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6186
{"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6193
{"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
6194
{"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
6215
{"divduo", XO(31,457,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6216
{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6218
{"divwuo", XO(31,459,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6219
{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6225
{"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
6226
{"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
6229
{"slbfee.", XRC(31,979,1), XRA_MASK, POWER6, 0, {RT, RB}},
arch/powerpc/xmon/ppc-opc.c
6246
{"nabso", XO(31,488,1,0), XORB_MASK, M601, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
6247
{"nabso.", XO(31,488,1,1), XORB_MASK, M601, 0, {RT, RA}},
arch/powerpc/xmon/ppc-opc.c
6249
{"divdo", XO(31,489,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6250
{"divdo.", XO(31,489,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6252
{"divwo", XO(31,491,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6253
{"divwo.", XO(31,491,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
arch/powerpc/xmon/ppc-opc.c
6283
{"lwz", OP(32), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
arch/powerpc/xmon/ppc-opc.c
6284
{"l", OP(32), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
arch/powerpc/xmon/ppc-opc.c
6286
{"lwzu", OP(33), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAL}},
arch/powerpc/xmon/ppc-opc.c
6287
{"lu", OP(33), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
arch/powerpc/xmon/ppc-opc.c
6289
{"lbz", OP(34), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
arch/powerpc/xmon/ppc-opc.c
6291
{"lbzu", OP(35), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
arch/powerpc/xmon/ppc-opc.c
6303
{"lhz", OP(40), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
arch/powerpc/xmon/ppc-opc.c
6305
{"lhzu", OP(41), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
arch/powerpc/xmon/ppc-opc.c
6307
{"lha", OP(42), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
arch/powerpc/xmon/ppc-opc.c
6309
{"lhau", OP(43), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
arch/powerpc/xmon/ppc-opc.c
6315
{"lmw", OP(46), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAM}},
arch/powerpc/xmon/ppc-opc.c
6316
{"lm", OP(46), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
arch/powerpc/xmon/ppc-opc.c
6347
{"ld", DSO(58,0), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
arch/powerpc/xmon/ppc-opc.c
6348
{"ldu", DSO(58,1), DS_MASK, PPC64, PPCVLE, {RT, DS, RAL}},
arch/powerpc/xmon/ppc-opc.c
6349
{"lwa", DSO(58,2), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
arch/powerpc/xmon/ppc-opc.c
6599
{"xsxexpdp", XX2VA(60,347,0),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}},
arch/powerpc/xmon/ppc-opc.c
6600
{"xsxsigdp", XX2VA(60,347,1),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}},
arch/powerpc/xmon/ppc-opc.c
7014
{"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
arch/powerpc/xmon/ppc-opc.c
7015
{"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
arch/powerpc/xmon/ppc-opc.c
7016
{"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
arch/powerpc/xmon/ppc-opc.c
7017
{"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
arch/powerpc/xmon/ppc-opc.c
7018
{"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
arch/powerpc/xmon/ppc-opc.c
7019
{"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
arch/powerpc/xmon/ppc-opc.c
7020
{"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
arch/powerpc/xmon/ppc-opc.c
7021
{"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
arch/powerpc/xmon/ppc-opc.c
7022
{"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
arch/powerpc/xmon/ppc-opc.c
7023
{"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
arch/powerpc/xmon/ppc-opc.c
7031
{"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
arch/powerpc/xmon/ppc-opc.c
7032
{"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
arch/powerpc/xmon/ppc-opc.c
7033
{"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
arch/powerpc/xmon/ppc-opc.c
7034
{"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
arch/powerpc/xmon/ppc-opc.c
7035
{"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
arch/powerpc/xmon/ppc-opc.c
7036
{"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
arch/powerpc/xmon/ppc-opc.c
7037
{"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
arch/powerpc/xmon/ppc-opc.c
7038
{"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
arch/powerpc/xmon/ppc-opc.c
7039
{"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
arch/powerpc/xmon/ppc-opc.c
7050
{"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}},
arch/powerpc/xmon/ppc-opc.c
7051
{"e_la", OP(7), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
arch/powerpc/xmon/ppc-opc.c
7052
{"e_sub16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, NSI}},
arch/powerpc/xmon/ppc-opc.c
7062
{"e_lbz", OP(12), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
arch/powerpc/xmon/ppc-opc.c
7063
{"e_stb", OP(13), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
arch/powerpc/xmon/ppc-opc.c
7064
{"e_lha", OP(14), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
arch/powerpc/xmon/ppc-opc.c
7076
{"e_lwz", OP(20), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
arch/powerpc/xmon/ppc-opc.c
7077
{"e_stw", OP(21), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
arch/powerpc/xmon/ppc-opc.c
7078
{"e_lhz", OP(22), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
arch/powerpc/xmon/ppc-opc.c
7079
{"e_sth", OP(23), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
arch/powerpc/xmon/ppc-opc.c
7103
{"e_li", LI20(28,0), LI20_MASK, PPCVLE, 0, {RT, IMM20}},
arch/powerpc/xmon/ppc-opc.c
7105
{"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RT, SH, MBE, ME}},
drivers/gpu/drm/radeon/sumo_dpm.c
212
rcu_pwr_gating_cntl |= RT(r_t) | IT(i_t);
drivers/media/platform/rockchip/rga/rga-hw.c
105
case RT:
drivers/media/platform/rockchip/rga/rga-hw.c
84
LT, RT, LB, RB,
drivers/media/platform/rockchip/rga/rga-hw.c
87
RT, LT, RB, LB,
drivers/media/platform/rockchip/rga/rga-hw.c
90
RB, LB, RT, LT,
drivers/media/platform/rockchip/rga/rga-hw.c
93
LB, RB, LT, RT,
drivers/pinctrl/pinctrl-st.c
161
#define ST_PINCONF_UNPACK_RT(conf) ST_PINCONF_UNPACK(conf, RT)
drivers/pinctrl/pinctrl-st.c
162
#define ST_PINCONF_PACK_RT(conf) ST_PINCONF_PACK(conf, 1, RT)
scripts/dtc/include-prefixes/arm/st/st-pincfg.h
51
#define SE_NICLK_IO (RT)
scripts/dtc/include-prefixes/arm/st/st-pincfg.h
56
#define SE_ICLK_IO (RT | INVERTCLK)
scripts/dtc/include-prefixes/arm/st/st-pincfg.h
61
#define DE_IO (RT | DOUBLE_EDGE)
scripts/dtc/include-prefixes/arm/st/st-pincfg.h
66
#define ICLK (RT | CLKNOTDATA | INVERTCLK)
scripts/dtc/include-prefixes/arm/st/st-pincfg.h
71
#define NICLK (RT | CLKNOTDATA)
