Symbol: RST_NR_PER_BANK
drivers/clk/clk-en7523.c
325
[EN7523_PCM1_ZSI_ISI_RST] = RST_NR_PER_BANK + 0,
drivers/clk/clk-en7523.c
326
[EN7523_FE_PDMA_RST] = RST_NR_PER_BANK + 1,
drivers/clk/clk-en7523.c
327
[EN7523_FE_QDMA_RST] = RST_NR_PER_BANK + 2,
drivers/clk/clk-en7523.c
328
[EN7523_PCM_SPIWP_RST] = RST_NR_PER_BANK + 4,
drivers/clk/clk-en7523.c
329
[EN7523_CRYPTO_RST] = RST_NR_PER_BANK + 6,
drivers/clk/clk-en7523.c
330
[EN7523_TIMER_RST] = RST_NR_PER_BANK + 8,
drivers/clk/clk-en7523.c
331
[EN7523_PCM1_RST] = RST_NR_PER_BANK + 11,
drivers/clk/clk-en7523.c
332
[EN7523_UART_RST] = RST_NR_PER_BANK + 12,
drivers/clk/clk-en7523.c
333
[EN7523_GPIO_RST] = RST_NR_PER_BANK + 13,
drivers/clk/clk-en7523.c
334
[EN7523_GDMA_RST] = RST_NR_PER_BANK + 14,
drivers/clk/clk-en7523.c
335
[EN7523_I2C_MASTER_RST] = RST_NR_PER_BANK + 16,
drivers/clk/clk-en7523.c
336
[EN7523_PCM2_ZSI_ISI_RST] = RST_NR_PER_BANK + 17,
drivers/clk/clk-en7523.c
337
[EN7523_SFC_RST] = RST_NR_PER_BANK + 18,
drivers/clk/clk-en7523.c
338
[EN7523_UART2_RST] = RST_NR_PER_BANK + 19,
drivers/clk/clk-en7523.c
339
[EN7523_GDMP_RST] = RST_NR_PER_BANK + 20,
drivers/clk/clk-en7523.c
340
[EN7523_FE_RST] = RST_NR_PER_BANK + 21,
drivers/clk/clk-en7523.c
341
[EN7523_USB_HOST_P0_RST] = RST_NR_PER_BANK + 22,
drivers/clk/clk-en7523.c
342
[EN7523_GSW_RST] = RST_NR_PER_BANK + 23,
drivers/clk/clk-en7523.c
343
[EN7523_SFC2_PCM_RST] = RST_NR_PER_BANK + 25,
drivers/clk/clk-en7523.c
344
[EN7523_PCIE0_RST] = RST_NR_PER_BANK + 26,
drivers/clk/clk-en7523.c
345
[EN7523_PCIE1_RST] = RST_NR_PER_BANK + 27,
drivers/clk/clk-en7523.c
346
[EN7523_PCIE_HB_RST] = RST_NR_PER_BANK + 29,
drivers/clk/clk-en7523.c
347
[EN7523_XPON_MAC_RST] = RST_NR_PER_BANK + 31,
drivers/clk/clk-en7523.c
382
[EN7581_PCM1_ZSI_ISI_RST] = RST_NR_PER_BANK + 0,
drivers/clk/clk-en7523.c
383
[EN7581_FE_PDMA_RST] = RST_NR_PER_BANK + 1,
drivers/clk/clk-en7523.c
384
[EN7581_FE_QDMA_RST] = RST_NR_PER_BANK + 2,
drivers/clk/clk-en7523.c
385
[EN7581_PCM_SPIWP_RST] = RST_NR_PER_BANK + 4,
drivers/clk/clk-en7523.c
386
[EN7581_CRYPTO_RST] = RST_NR_PER_BANK + 6,
drivers/clk/clk-en7523.c
387
[EN7581_TIMER_RST] = RST_NR_PER_BANK + 8,
drivers/clk/clk-en7523.c
388
[EN7581_PCM1_RST] = RST_NR_PER_BANK + 11,
drivers/clk/clk-en7523.c
389
[EN7581_UART_RST] = RST_NR_PER_BANK + 12,
drivers/clk/clk-en7523.c
390
[EN7581_GPIO_RST] = RST_NR_PER_BANK + 13,
drivers/clk/clk-en7523.c
391
[EN7581_GDMA_RST] = RST_NR_PER_BANK + 14,
drivers/clk/clk-en7523.c
392
[EN7581_I2C_MASTER_RST] = RST_NR_PER_BANK + 16,
drivers/clk/clk-en7523.c
393
[EN7581_PCM2_ZSI_ISI_RST] = RST_NR_PER_BANK + 17,
drivers/clk/clk-en7523.c
394
[EN7581_SFC_RST] = RST_NR_PER_BANK + 18,
drivers/clk/clk-en7523.c
395
[EN7581_UART2_RST] = RST_NR_PER_BANK + 19,
drivers/clk/clk-en7523.c
396
[EN7581_GDMP_RST] = RST_NR_PER_BANK + 20,
drivers/clk/clk-en7523.c
397
[EN7581_FE_RST] = RST_NR_PER_BANK + 21,
drivers/clk/clk-en7523.c
398
[EN7581_USB_HOST_P0_RST] = RST_NR_PER_BANK + 22,
drivers/clk/clk-en7523.c
399
[EN7581_GSW_RST] = RST_NR_PER_BANK + 23,
drivers/clk/clk-en7523.c
400
[EN7581_SFC2_PCM_RST] = RST_NR_PER_BANK + 25,
drivers/clk/clk-en7523.c
401
[EN7581_PCIE0_RST] = RST_NR_PER_BANK + 26,
drivers/clk/clk-en7523.c
402
[EN7581_PCIE1_RST] = RST_NR_PER_BANK + 27,
drivers/clk/clk-en7523.c
403
[EN7581_CPU_TIMER_RST] = RST_NR_PER_BANK + 28,
drivers/clk/clk-en7523.c
404
[EN7581_PCIE_HB_RST] = RST_NR_PER_BANK + 29,
drivers/clk/clk-en7523.c
405
[EN7581_XPON_MAC_RST] = RST_NR_PER_BANK + 31,
drivers/clk/clk-en7523.c
656
void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK];
drivers/clk/clk-en7523.c
661
val |= BIT(id % RST_NR_PER_BANK);
drivers/clk/clk-en7523.c
663
val &= ~BIT(id % RST_NR_PER_BANK);
drivers/clk/clk-en7523.c
685
void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK];
drivers/clk/clk-en7523.c
687
return !!(readl(addr) & BIT(id % RST_NR_PER_BANK));
drivers/clk/mediatek/clk-mt6735-infracfg.c
52
[MT6735_INFRA_RST0_EMI_REG] = 0 * RST_NR_PER_BANK + 0,
drivers/clk/mediatek/clk-mt6735-infracfg.c
53
[MT6735_INFRA_RST0_DRAMC0_AO] = 0 * RST_NR_PER_BANK + 1,
drivers/clk/mediatek/clk-mt6735-infracfg.c
54
[MT6735_INFRA_RST0_AP_CIRQ_EINT] = 0 * RST_NR_PER_BANK + 3,
drivers/clk/mediatek/clk-mt6735-infracfg.c
55
[MT6735_INFRA_RST0_APXGPT] = 0 * RST_NR_PER_BANK + 4,
drivers/clk/mediatek/clk-mt6735-infracfg.c
56
[MT6735_INFRA_RST0_SCPSYS] = 0 * RST_NR_PER_BANK + 5,
drivers/clk/mediatek/clk-mt6735-infracfg.c
57
[MT6735_INFRA_RST0_KP] = 0 * RST_NR_PER_BANK + 6,
drivers/clk/mediatek/clk-mt6735-infracfg.c
58
[MT6735_INFRA_RST0_PMIC_WRAP] = 0 * RST_NR_PER_BANK + 7,
drivers/clk/mediatek/clk-mt6735-infracfg.c
59
[MT6735_INFRA_RST0_CLDMA_AO_TOP] = 0 * RST_NR_PER_BANK + 8,
drivers/clk/mediatek/clk-mt6735-infracfg.c
60
[MT6735_INFRA_RST0_USBSIF_TOP] = 0 * RST_NR_PER_BANK + 9,
drivers/clk/mediatek/clk-mt6735-infracfg.c
61
[MT6735_INFRA_RST0_EMI] = 0 * RST_NR_PER_BANK + 16,
drivers/clk/mediatek/clk-mt6735-infracfg.c
62
[MT6735_INFRA_RST0_CCIF] = 0 * RST_NR_PER_BANK + 17,
drivers/clk/mediatek/clk-mt6735-infracfg.c
63
[MT6735_INFRA_RST0_DRAMC0] = 0 * RST_NR_PER_BANK + 18,
drivers/clk/mediatek/clk-mt6735-infracfg.c
64
[MT6735_INFRA_RST0_EMI_AO_REG] = 0 * RST_NR_PER_BANK + 19,
drivers/clk/mediatek/clk-mt6735-infracfg.c
65
[MT6735_INFRA_RST0_CCIF_AO] = 0 * RST_NR_PER_BANK + 20,
drivers/clk/mediatek/clk-mt6735-infracfg.c
66
[MT6735_INFRA_RST0_TRNG] = 0 * RST_NR_PER_BANK + 21,
drivers/clk/mediatek/clk-mt6735-infracfg.c
67
[MT6735_INFRA_RST0_SYS_CIRQ] = 0 * RST_NR_PER_BANK + 22,
drivers/clk/mediatek/clk-mt6735-infracfg.c
68
[MT6735_INFRA_RST0_GCE] = 0 * RST_NR_PER_BANK + 23,
drivers/clk/mediatek/clk-mt6735-infracfg.c
69
[MT6735_INFRA_RST0_M4U] = 0 * RST_NR_PER_BANK + 24,
drivers/clk/mediatek/clk-mt6735-infracfg.c
70
[MT6735_INFRA_RST0_CCIF1] = 0 * RST_NR_PER_BANK + 25,
drivers/clk/mediatek/clk-mt6735-infracfg.c
71
[MT6735_INFRA_RST0_CLDMA_TOP_PD] = 0 * RST_NR_PER_BANK + 26
drivers/clk/mediatek/clk-mt6735-pericfg.c
65
[MT6735_PERI_RST0_UART0] = 0 * RST_NR_PER_BANK + 0,
drivers/clk/mediatek/clk-mt6735-pericfg.c
66
[MT6735_PERI_RST0_UART1] = 0 * RST_NR_PER_BANK + 1,
drivers/clk/mediatek/clk-mt6735-pericfg.c
67
[MT6735_PERI_RST0_UART2] = 0 * RST_NR_PER_BANK + 2,
drivers/clk/mediatek/clk-mt6735-pericfg.c
68
[MT6735_PERI_RST0_UART3] = 0 * RST_NR_PER_BANK + 3,
drivers/clk/mediatek/clk-mt6735-pericfg.c
69
[MT6735_PERI_RST0_UART4] = 0 * RST_NR_PER_BANK + 4,
drivers/clk/mediatek/clk-mt6735-pericfg.c
70
[MT6735_PERI_RST0_BTIF] = 0 * RST_NR_PER_BANK + 6,
drivers/clk/mediatek/clk-mt6735-pericfg.c
71
[MT6735_PERI_RST0_DISP_PWM_PERI] = 0 * RST_NR_PER_BANK + 7,
drivers/clk/mediatek/clk-mt6735-pericfg.c
72
[MT6735_PERI_RST0_PWM] = 0 * RST_NR_PER_BANK + 8,
drivers/clk/mediatek/clk-mt6735-pericfg.c
73
[MT6735_PERI_RST0_AUXADC] = 0 * RST_NR_PER_BANK + 10,
drivers/clk/mediatek/clk-mt6735-pericfg.c
74
[MT6735_PERI_RST0_DMA] = 0 * RST_NR_PER_BANK + 11,
drivers/clk/mediatek/clk-mt6735-pericfg.c
75
[MT6735_PERI_RST0_IRDA] = 0 * RST_NR_PER_BANK + 12,
drivers/clk/mediatek/clk-mt6735-pericfg.c
76
[MT6735_PERI_RST0_IRTX] = 0 * RST_NR_PER_BANK + 13,
drivers/clk/mediatek/clk-mt6735-pericfg.c
77
[MT6735_PERI_RST0_THERM] = 0 * RST_NR_PER_BANK + 16,
drivers/clk/mediatek/clk-mt6735-pericfg.c
78
[MT6735_PERI_RST0_MSDC2] = 0 * RST_NR_PER_BANK + 17,
drivers/clk/mediatek/clk-mt6735-pericfg.c
79
[MT6735_PERI_RST0_MSDC3] = 0 * RST_NR_PER_BANK + 18,
drivers/clk/mediatek/clk-mt6735-pericfg.c
80
[MT6735_PERI_RST0_MSDC0] = 0 * RST_NR_PER_BANK + 19,
drivers/clk/mediatek/clk-mt6735-pericfg.c
81
[MT6735_PERI_RST0_MSDC1] = 0 * RST_NR_PER_BANK + 20,
drivers/clk/mediatek/clk-mt6735-pericfg.c
82
[MT6735_PERI_RST0_I2C0] = 0 * RST_NR_PER_BANK + 22,
drivers/clk/mediatek/clk-mt6735-pericfg.c
83
[MT6735_PERI_RST0_I2C1] = 0 * RST_NR_PER_BANK + 23,
drivers/clk/mediatek/clk-mt6735-pericfg.c
84
[MT6735_PERI_RST0_I2C2] = 0 * RST_NR_PER_BANK + 24,
drivers/clk/mediatek/clk-mt6735-pericfg.c
85
[MT6735_PERI_RST0_I2C3] = 0 * RST_NR_PER_BANK + 25,
drivers/clk/mediatek/clk-mt6735-pericfg.c
86
[MT6735_PERI_RST0_USB] = 0 * RST_NR_PER_BANK + 28,
drivers/clk/mediatek/clk-mt6735-pericfg.c
88
[MT6735_PERI_RST1_SPI0] = 1 * RST_NR_PER_BANK + 1,
drivers/clk/mediatek/clk-mt6735-vdecsys.c
44
[MT6735_VDEC_RST0_VDEC] = 0 * RST_NR_PER_BANK + 0,
drivers/clk/mediatek/clk-mt6735-vdecsys.c
45
[MT6735_VDEC_RST1_SMI_LARB1] = 1 * RST_NR_PER_BANK + 0,
drivers/clk/mediatek/clk-mt6795-infracfg.c
65
[MT6795_INFRA_RST0_SCPSYS_RST] = 0 * RST_NR_PER_BANK + 5,
drivers/clk/mediatek/clk-mt6795-infracfg.c
66
[MT6795_INFRA_RST0_PMIC_WRAP_RST] = 0 * RST_NR_PER_BANK + 7,
drivers/clk/mediatek/clk-mt6795-infracfg.c
67
[MT6795_INFRA_RST1_MIPI_DSI_RST] = 1 * RST_NR_PER_BANK + 4,
drivers/clk/mediatek/clk-mt6795-infracfg.c
68
[MT6795_INFRA_RST1_MIPI_CSI_RST] = 1 * RST_NR_PER_BANK + 7,
drivers/clk/mediatek/clk-mt6795-infracfg.c
69
[MT6795_INFRA_RST1_MM_IOMMU_RST] = 1 * RST_NR_PER_BANK + 15,
drivers/clk/mediatek/clk-mt7988-infracfg.c
262
[MT7988_INFRA_RST0_PEXTP_MAC_SWRST] = 0 * RST_NR_PER_BANK + 6,
drivers/clk/mediatek/clk-mt7988-infracfg.c
263
[MT7988_INFRA_RST1_THERM_CTRL_SWRST] = 1 * RST_NR_PER_BANK + 9,
drivers/clk/mediatek/clk-mt8186-infra_ao.c
204
[MT8186_INFRA_THERMAL_CTRL_RST] = 0 * RST_NR_PER_BANK + 0,
drivers/clk/mediatek/clk-mt8186-infra_ao.c
205
[MT8186_INFRA_PTP_CTRL_RST] = 1 * RST_NR_PER_BANK + 0,
drivers/clk/mediatek/clk-mt8188-infra_ao.c
189
[MT8188_INFRA_RST1_THERMAL_MCU_RST] = 1 * RST_NR_PER_BANK + 2,
drivers/clk/mediatek/clk-mt8188-infra_ao.c
190
[MT8188_INFRA_RST1_THERMAL_CTRL_RST] = 1 * RST_NR_PER_BANK + 4,
drivers/clk/mediatek/clk-mt8188-infra_ao.c
191
[MT8188_INFRA_RST3_PTP_CTRL_RST] = 3 * RST_NR_PER_BANK + 5,
drivers/clk/mediatek/clk-mt8192.c
951
[MT8192_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0,
drivers/clk/mediatek/clk-mt8192.c
952
[MT8192_INFRA_RST2_PEXTP_PHY_SWRST] = 2 * RST_NR_PER_BANK + 15,
drivers/clk/mediatek/clk-mt8192.c
953
[MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5,
drivers/clk/mediatek/clk-mt8192.c
954
[MT8192_INFRA_RST4_PCIE_TOP_SWRST] = 4 * RST_NR_PER_BANK + 1,
drivers/clk/mediatek/clk-mt8192.c
955
[MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 12,
drivers/clk/mediatek/clk-mt8195-infra_ao.c
202
[MT8195_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0,
drivers/clk/mediatek/clk-mt8195-infra_ao.c
203
[MT8195_INFRA_RST2_USBSIF_P1_SWRST] = 2 * RST_NR_PER_BANK + 18,
drivers/clk/mediatek/clk-mt8195-infra_ao.c
204
[MT8195_INFRA_RST2_PCIE_P0_SWRST] = 2 * RST_NR_PER_BANK + 26,
drivers/clk/mediatek/clk-mt8195-infra_ao.c
205
[MT8195_INFRA_RST2_PCIE_P1_SWRST] = 2 * RST_NR_PER_BANK + 27,
drivers/clk/mediatek/clk-mt8195-infra_ao.c
206
[MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5,
drivers/clk/mediatek/clk-mt8195-infra_ao.c
207
[MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 10,
drivers/clk/mediatek/clk-mt8196-ufs_ao.c
72
[MT8196_UFSAO_RST1_UFS_UNIPRO] = 1 * RST_NR_PER_BANK + 0,
drivers/clk/mediatek/clk-mt8196-ufs_ao.c
73
[MT8196_UFSAO_RST1_UFS_CRYPTO] = 1 * RST_NR_PER_BANK + 1,
drivers/clk/mediatek/clk-mt8196-ufs_ao.c
74
[MT8196_UFSAO_RST1_UFSHCI] = 1 * RST_NR_PER_BANK + 2,
drivers/clk/mediatek/reset.c
161
data->rcdev.nr_resets = desc->rst_bank_nr * RST_NR_PER_BANK;
drivers/clk/mediatek/reset.c
27
data->desc->rst_bank_ofs[id / RST_NR_PER_BANK],
drivers/clk/mediatek/reset.c
28
BIT(id % RST_NR_PER_BANK), val);
drivers/clk/mediatek/reset.c
61
data->desc->rst_bank_ofs[id / RST_NR_PER_BANK] +
drivers/clk/mediatek/reset.c
63
BIT(id % RST_NR_PER_BANK));