RSTV0910_P2_VTH12
write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]);
write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]);
write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]);
write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]);
write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]);
write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]);
write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]);
write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]);
write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]);
write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]);
write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]);
write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]);