B24
#define CR B24 + 1
{"e_b", BD24(30,0,0), BD24_MASK, PPCVLE, 0, {B24}},
{"e_bl", BD24(30,0,1), BD24_MASK, PPCVLE, 0, {B24}},
ASPEED_PINCTRL_PIN(B24),
{ PIN_CONFIG_POWER_SOURCE, { F24, B24 }, SCU458, BIT_MASK(5)},
{ PIN_CONFIG_DRIVE_STRENGTH, { F24, B24 }, SCU458, GENMASK(3, 2)},
SIG_EXPR_LIST_DECL_SESG(B24, NRTS4, NRTS4, SIG_DESC_SET(SCU414, 7));
SIG_EXPR_LIST_DECL_SESG(B24, RGMII4RXD3, RGMII4, SIG_DESC_SET(SCU4B4, 7),
SIG_EXPR_LIST_DECL_SESG(B24, RMII4RXER, RMII4, SIG_DESC_SET(SCU4B4, 7),
PIN_DECL_3(B24, GPIOE7, NRTS4, RGMII4RXD3, RMII4RXER);
FUNC_GROUP_DECL(NRTS4, B24);
B24);
GROUP_DECL(RMII4, F24, E23, E24, E25, C25, C24, B26, B25, B24);
GROUP_DECL(NCSI4, E23, E24, E25, C25, C24, B26, B25, B24);