arch/riscv/include/asm/insn-def.h

189

__RD(0), RS1(vaddr), RS2(asid))

arch/riscv/include/asm/insn-def.h

193

__RD(0), RS1(gaddr), RS2(vmid))

arch/riscv/include/asm/insn-def.h

238

__RD(0), RS1(addr), RS2(src))

arch/riscv/include/asm/insn-def.h

242

__RD(0), RS1(addr), RS2(src))

arch/riscv/include/asm/insn-def.h

246

__RD(0), RS1(addr), RS2(src))

arch/riscv/include/asm/insn-def.h

250

__RD(0), RS1(addr), RS2(src))

arch/riscv/include/asm/insn-def.h

254

__RD(0), RS1(addr), RS2(src))

arch/riscv/include/asm/insn-def.h

258

__RD(0), RS1(addr), RS2(src))

arch/riscv/include/asm/insn-def.h

271

__RD(0), RS1(addr), RS2(src))

arch/riscv/include/asm/insn-def.h

275

__RD(0), RS1(addr), RS2(src))

arch/riscv/include/asm/insn-def.h

292

__RD(0), RS1(vaddr), RS2(asid))

arch/riscv/include/asm/insn-def.h

304

__RD(0), RS1(vaddr), RS2(asid))

arch/riscv/include/asm/insn-def.h

308

__RD(0), RS1(gaddr), RS2(vmid))

arch/sparc/include/asm/opcodes.h

19

.word (F3F(2,0x36,0x147)|RS1(a)|RS2(b)|RD(c));

arch/sparc/include/asm/opcodes.h

31

.word (F3F(2, 0x19, 0)|RS1(a)|RS2(b)|RS3(c)|RD(d));

arch/sparc/include/asm/opcodes.h

33

.word (F3F(2, 0x19, 1)|RS1(a)|RS2(b)|RS3(c)|RD(d));

arch/sparc/include/asm/opcodes.h

35

.word (F3F(2, 0x19, 2)|RS1(a)|RS2(b)|RS3(c)|RD(d));

arch/sparc/include/asm/opcodes.h

37

.word (F3F(2, 0x19, 3)|RS1(a)|RS2(b)|RS3(c)|RD(d));

arch/sparc/include/asm/opcodes.h

39

.word (F3F(2, 0x19, 4)|RS1(a)|RS2(b)|RS3(c)|RD(d));

arch/sparc/include/asm/opcodes.h

41

.word (F3F(2, 0x19, 5)|RS1(a)|RS2(b)|RS3(c)|RD(d));

arch/sparc/include/asm/opcodes.h

43

.word (F3F(2, 0x19, 6)|RS1(a)|RS2(b)|RS3(c)|RD(d));

arch/sparc/include/asm/opcodes.h

45

.word (F3F(2, 0x19, 7)|RS1(a)|RS2(b)|RS3(c)|RD(d));

arch/sparc/include/asm/opcodes.h

47

.word (F3F(2, 0x19, 8)|RS1(a)|RS2(b)|IMM5_9(c)|RD(d));

arch/sparc/include/asm/opcodes.h

49

.word (F3F(2, 0x36, 0x130)|RS1(a)|RS2(b)|RD(c));

arch/sparc/include/asm/opcodes.h

51

.word (F3F(2, 0x36, 0x131)|RS1(a)|RS2(b)|RD(c));

arch/sparc/include/asm/opcodes.h

60

.word (F3F(2, 0x19, 0x009)|RS1(a)|RS2(b)|RS3(c)|RD(d));

arch/sparc/include/asm/opcodes.h

63

.word (F3F(2, 0x19, 0x00c)|RS1(a)|RS2(b)|RS3(c)|RD(d));

arch/sparc/include/asm/opcodes.h

65

.word (F3F(2, 0x36, 0x13c)|RS1(a)|RS2(b)|RD(c));

arch/sparc/include/asm/opcodes.h

67

.word (F3F(2, 0x36, 0x13d)|RS1(a)|RS2(b)|RD(c));

arch/sparc/kernel/visemul.c

299

maybe_flush_windows(RS1(insn), RS2(insn), RD(insn), 0);

arch/sparc/kernel/visemul.c

301

orig_rs2 = rs2 = fetch_reg(RS2(insn), regs);

arch/sparc/kernel/visemul.c

377

maybe_flush_windows(RS1(insn), RS2(insn), RD(insn), 0);

arch/sparc/kernel/visemul.c

379

rs2 = fetch_reg(RS2(insn), regs);

arch/sparc/kernel/visemul.c

410

maybe_flush_windows(RS1(insn), RS2(insn), RD(insn), 0);

arch/sparc/kernel/visemul.c

412

rs2 = fetch_reg(RS2(insn), regs);

arch/sparc/kernel/visemul.c

431

rs2 = fpd_regval(f, RS2(insn));

arch/sparc/kernel/visemul.c

455

rs2 = fpd_regval(f, RS2(insn));

arch/sparc/kernel/visemul.c

488

rs2 = fpd_regval(f, RS2(insn));

arch/sparc/kernel/visemul.c

511

rs2 = fpd_regval(f, RS2(insn));

arch/sparc/kernel/visemul.c

533

rs2 = fpd_regval(f, RS2(insn));

arch/sparc/kernel/visemul.c

556

rs2 = fps_regval(f, RS2(insn));

arch/sparc/kernel/visemul.c

573

rs2 = fps_regval(f, RS2(insn));

arch/sparc/kernel/visemul.c

599

rs2 = fpd_regval(f, RS2(insn));

arch/sparc/kernel/visemul.c

624

rs2 = fps_regval(f, RS2(insn));

arch/sparc/kernel/visemul.c

648

rs2 = fpd_regval(f, RS2(insn));

arch/sparc/kernel/visemul.c

678

rs2 = fps_regval(f, RS2(insn));

arch/sparc/kernel/visemul.c

711

rs2 = fpd_regval(f, RS2(insn));

arch/sparc/net/bpf_jit_comp_32.c

113

*prog++ = SUB | RS1(G0) | RS2(r_A) | RD(r_A); \

arch/sparc/net/bpf_jit_comp_32.c

118

*prog++ = OR | RS1(G0) | RS2(FROM) | RD(TO); \

arch/sparc/net/bpf_jit_comp_32.c

123

*prog++ = OR | RS1(G0) | RS2(G0) | RD(REG); \

arch/sparc/net/bpf_jit_comp_32.c

140

*prog++ = OPCODE | RS1(r_A) | RS2(r_X) | RD(r_A); \

arch/sparc/net/bpf_jit_comp_32.c

166

*prog++ = _insn | RS2(r_TMP); \

arch/sparc/net/bpf_jit_comp_32.c

262

*prog++ = (SUBCC | RS1(R1) | RS2(R2) | RD(G0))

arch/sparc/net/bpf_jit_comp_32.c

268

*prog++ = (ANDCC | RS1(R1) | RS2(R2) | RD(G0))

arch/sparc/net/bpf_jit_comp_32.c

274

*prog++ = (SUB | RS1(R1) | RS2(R2) | RD(R3))

arch/sparc/net/bpf_jit_comp_32.c

280

*prog++ = (ADD | RS1(R1) | RS2(R2) | RD(R3))

arch/sparc/net/bpf_jit_comp_32.c

286

*prog++ = (AND | RS1(R1) | RS2(R2) | RD(R3))

arch/sparc/net/bpf_jit_comp_64.c

1057

emit(ST64 | RS1(tmp) | RS2(G0) | RD(dst), ctx);

arch/sparc/net/bpf_jit_comp_64.c

1058

emit(LD64A | ASI(ASI_PL) | RS1(tmp) | RS2(G0) | RD(dst), ctx);

arch/sparc/net/bpf_jit_comp_64.c

1129

emit(SUB | RS1(dst) | RS2(tmp) | RD(dst), ctx);

arch/sparc/net/bpf_jit_comp_64.c

1136

emit(div | RS1(dst) | RS2(tmp1) | RD(tmp), ctx);

arch/sparc/net/bpf_jit_comp_64.c

1137

emit(MULX | RS1(tmp) | RS2(tmp1) | RD(tmp), ctx);

arch/sparc/net/bpf_jit_comp_64.c

1138

emit(SUB | RS1(dst) | RS2(tmp) | RD(dst), ctx);

arch/sparc/net/bpf_jit_comp_64.c

1283

rs2 = RS2(tmp);

arch/sparc/net/bpf_jit_comp_64.c

1329

rs2 = RS2(tmp);

arch/sparc/net/bpf_jit_comp_64.c

1366

rs2 = RS2(tmp);

arch/sparc/net/bpf_jit_comp_64.c

1393

emit(LD32 | RS1(tmp) | RS2(G0) | RD(tmp2), ctx);

arch/sparc/net/bpf_jit_comp_64.c

1395

emit(CAS | ASI(ASI_P) | RS1(tmp) | RS2(tmp2) | RD(tmp3), ctx);

arch/sparc/net/bpf_jit_comp_64.c

1421

emit(LD64 | RS1(tmp) | RS2(G0) | RD(tmp2), ctx);

arch/sparc/net/bpf_jit_comp_64.c

1423

emit(CASX | ASI(ASI_P) | RS1(tmp) | RS2(tmp2) | RD(tmp3), ctx);

arch/sparc/net/bpf_jit_comp_64.c

263

emit(OR | RS1(G0) | RS2(from) | RD(to), ctx);

arch/sparc/net/bpf_jit_comp_64.c

290

emit(opcode | RS1(dst) | RS2(src) | RD(dst), ctx);

arch/sparc/net/bpf_jit_comp_64.c

295

emit(opcode | RS1(a) | RS2(b) | RD(c), ctx);

arch/sparc/net/bpf_jit_comp_64.c

313

emit(insn | RS2(tmp), ctx);

arch/sparc/net/bpf_jit_comp_64.c

332

emit(insn | RS2(tmp), ctx);

arch/sparc/net/bpf_jit_comp_64.c

613

emit(OR | RS1(dest) | RS2(tmp) | RD(dest), ctx);

arch/sparc/net/bpf_jit_comp_64.c

632

emit(cb_opc | WDISP10(off << 2) | RS1(dst) | RS2(src), ctx);

arch/sparc/net/bpf_jit_comp_64.c

647

emit(SUBCC | RS1(R1) | RS2(R2) | RD(G0), CTX)

arch/sparc/net/bpf_jit_comp_64.c

653

emit(ANDCC | RS1(R1) | RS2(R2) | RD(G0), CTX)

arch/sparc/net/bpf_jit_comp_64.c

847

emit(RESTORE | RS1(bpf2sparc[BPF_REG_0]) | RS2(G0) | RD(O0), ctx);

arch/sparc/net/bpf_jit_comp_64.c

998

emit(SUB | RS1(0) | RS2(dst) | RD(dst), ctx);