RS1
__RD(0), RS1(vaddr), RS2(asid))
__RD(0), RS1(gaddr), RS2(vmid))
RD(dest), RS1(addr), __RS2(3))
RD(dest), RS1(addr), __RS2(0))
RD(dest), RS1(addr), __RS2(0))
RD(dest), RS1(addr), __RS2(0))
RD(dest), RS1(addr), __RS2(0))
RD(dest), RS1(addr), __RS2(0))
RD(dest), RS1(addr), __RS2(0))
RD(dest), RS1(addr), __RS2(0))
RD(dest), RS1(addr), __RS2(0))
__RD(0), RS1(addr), RS2(src))
__RD(0), RS1(addr), RS2(src))
__RD(0), RS1(addr), RS2(src))
__RD(0), RS1(addr), RS2(src))
__RD(0), RS1(addr), RS2(src))
__RD(0), RS1(addr), RS2(src))
RD(dest), RS1(addr), __RS2(0))
RD(dest), RS1(addr), __RS2(0))
__RD(0), RS1(addr), RS2(src))
__RD(0), RS1(addr), RS2(src))
__RD(0), RS1(vaddr), RS2(asid))
__RD(0), RS1(vaddr), RS2(asid))
__RD(0), RS1(gaddr), RS2(vmid))
RS1(base), SIMM12(0))
RS1(base), SIMM12(1))
RS1(base), SIMM12(2))
RS1(base), SIMM12(4))
SIMM12((offset) & 0xfe0), RS1(base))
SIMM12((offset) & 0xfe0), RS1(base))
SIMM12((offset) & 0xfe0), RS1(base))
.word (F3F(2,0x36,0x147)|RS1(a)|RS2(b)|RD(c));
.word (F3F(2, 0x19, 0)|RS1(a)|RS2(b)|RS3(c)|RD(d));
.word (F3F(2, 0x19, 1)|RS1(a)|RS2(b)|RS3(c)|RD(d));
.word (F3F(2, 0x19, 2)|RS1(a)|RS2(b)|RS3(c)|RD(d));
.word (F3F(2, 0x19, 3)|RS1(a)|RS2(b)|RS3(c)|RD(d));
.word (F3F(2, 0x19, 4)|RS1(a)|RS2(b)|RS3(c)|RD(d));
.word (F3F(2, 0x19, 5)|RS1(a)|RS2(b)|RS3(c)|RD(d));
.word (F3F(2, 0x19, 6)|RS1(a)|RS2(b)|RS3(c)|RD(d));
.word (F3F(2, 0x19, 7)|RS1(a)|RS2(b)|RS3(c)|RD(d));
.word (F3F(2, 0x19, 8)|RS1(a)|RS2(b)|IMM5_9(c)|RD(d));
.word (F3F(2, 0x36, 0x130)|RS1(a)|RS2(b)|RD(c));
.word (F3F(2, 0x36, 0x131)|RS1(a)|RS2(b)|RD(c));
.word (F3F(2, 0x36, 0x134)|RS1(a)|RD(b));
.word (F3F(2, 0x36, 0x135)|RS1(a)|RD(b));
.word (F3F(2, 0x36, 0x136)|RS1(a)|IMM5_0(b)|RD(c));
.word (F3F(2, 0x19, 0x009)|RS1(a)|RS2(b)|RS3(c)|RD(d));
.word (F3F(2, 0x19, 0x00c)|RS1(a)|RS2(b)|RS3(c)|RD(d));
.word (F3F(2, 0x36, 0x13c)|RS1(a)|RS2(b)|RD(c));
.word (F3F(2, 0x36, 0x13d)|RS1(a)|RS2(b)|RD(c));
maybe_flush_windows(RS1(insn), RS2(insn), RD(insn), 0);
orig_rs1 = rs1 = fetch_reg(RS1(insn), regs);
maybe_flush_windows(RS1(insn), RS2(insn), RD(insn), 0);
rs1 = fetch_reg(RS1(insn), regs);
maybe_flush_windows(RS1(insn), RS2(insn), RD(insn), 0);
rs1 = fetch_reg(RS1(insn), regs);
rs1 = fpd_regval(f, RS1(insn));
rs1 = fpd_regval(f, RS1(insn));
rs1 = fpd_regval(f, RS1(insn));
rs1 = fps_regval(f, RS1(insn));
rs1 = fps_regval(f, RS1(insn));
rs1 = fps_regval(f, RS1(insn));
rs1 = fpd_regval(f, RS1(insn));
rs1 = fps_regval(f, RS1(insn));
rs1 = fpd_regval(f, RS1(insn));
*prog++ = SUB | RS1(G0) | RS2(r_A) | RD(r_A); \
*prog++ = OR | RS1(G0) | RS2(FROM) | RD(TO); \
*prog++ = OR | RS1(G0) | RS2(G0) | RD(REG); \
*prog++ = OPCODE | RS1(r_A) | RS2(r_X) | RD(r_A); \
_insn |= RS1(r_A) | RD(r_A); \
*prog++ = OR | IMMED | RS1(G0) | S13(K) | RD(DEST); \
*prog++ = LDPTRI | RS1(BASE) | S13(_off) | RD(DEST); \
*prog++ = LD32I | RS1(BASE) | S13(_off) | RD(DEST); \
*prog++ = LD16I | RS1(BASE) | S13(_off) | RD(DEST); \
*prog++ = LD8I | RS1(BASE) | S13(_off) | RD(DEST); \
do { *prog++ = LD32I | RS1(SP) | S13(BIAS - (OFF)) | RD(DEST); \
do { *prog++ = ST32I | RS1(SP) | S13(BIAS - (OFF)) | RD(SRC); \
*prog++ = (JMPL | IMMED | RS1(BASE) | S13(IMM_OFF) | RD(LREG))
#define emit_write_y(REG) *prog++ = WR_Y | IMMED | RS1(REG) | S13(0)
*prog++ = (SUBCC | RS1(R1) | RS2(R2) | RD(G0))
*prog++ = (SUBCC | IMMED | RS1(R1) | S13(IMM) | RD(G0));
*prog++ = (ANDCC | RS1(R1) | RS2(R2) | RD(G0))
*prog++ = (ANDCC | IMMED | RS1(R1) | S13(IMM) | RD(G0));
*prog++ = (SUB | RS1(R1) | RS2(R2) | RD(R3))
*prog++ = (SUB | IMMED | RS1(R1) | S13(IMM) | RD(R3))
*prog++ = (ADD | RS1(R1) | RS2(R2) | RD(R3))
*prog++ = (ADD | IMMED | RS1(R1) | S13(IMM) | RD(R3))
*prog++ = (AND | RS1(R1) | RS2(R2) | RD(R3))
*prog++ = (AND | IMMED | RS1(R1) | S13(IMM) | RD(R3))
*prog++ = (SUB | IMMED | RS1(SP) | S13(SZ) | RD(SP))
*prog++ = (ADD | IMMED | RS1(SP) | S13(SZ) | RD(SP))
(F3(2, 0x02) | IMMED | RS1(REG) | ((K) & 0x3ff) | RD(REG))
emit(ST64 | RS1(tmp) | RS2(G0) | RD(dst), ctx);
emit(LD64A | ASI(ASI_PL) | RS1(tmp) | RS2(G0) | RD(dst), ctx);
emit(div | IMMED | RS1(dst) | S13(imm) | RD(tmp), ctx);
emit(MULX | IMMED | RS1(tmp) | S13(imm) | RD(tmp), ctx);
emit(SUB | RS1(dst) | RS2(tmp) | RD(dst), ctx);
emit(div | RS1(dst) | RS2(tmp1) | RD(tmp), ctx);
emit(MULX | RS1(tmp) | RS2(tmp1) | RD(tmp), ctx);
emit(SUB | RS1(dst) | RS2(tmp) | RD(dst), ctx);
emit(opcode | RS1(src) | rs2 | RD(dst), ctx);
emit(opcode | RS1(dst) | rs2 | RD(tmp2), ctx);
emit(opcode | RS1(dst) | rs2 | RD(src), ctx);
(F3(2, 0x02) | IMMED | RS1(REG) | ((K) & 0x3ff) | RD(REG))
emit(LD32 | RS1(tmp) | RS2(G0) | RD(tmp2), ctx);
emit(CAS | ASI(ASI_P) | RS1(tmp) | RS2(tmp2) | RD(tmp3), ctx);
emit(LD64 | RS1(tmp) | RS2(G0) | RD(tmp2), ctx);
emit(CASX | ASI(ASI_P) | RS1(tmp) | RS2(tmp2) | RD(tmp3), ctx);
emit(OR | RS1(G0) | RS2(from) | RD(to), ctx);
emit(XOR | IMMED | RS1(reg) | S13(lbits) | RD(reg), ctx);
emit(opcode | RS1(dst) | RS2(src) | RD(dst), ctx);
emit(opcode | RS1(a) | RS2(b) | RD(c), ctx);
insn |= RS1(dst) | RD(dst);
insn |= RS1(src) | RD(dst);
emit(OR | IMMED | RS1(G0) | S13(K) | RD(dest), ctx);
emit(OR | IMMED | RS1(G0) | S13(K) | RD(dest), ctx);
emit(OR | IMMED | RS1(G0) | S13(K) | RD(dest), ctx);
emit(OR | IMMED | RS1(dest) | S13(low_imm) | RD(dest), ctx);
emit(OR | IMMED | RS1(G0) | S13(the_const) | RD(dest), ctx);
emit(OR | IMMED | RS1(G0) | S13(fast_int) | RD(dest), ctx);
emit(XOR | IMMED | RS1(dest) | S13(low_bits) | RD(dest), ctx);
emit(OR | RS1(dest) | RS2(tmp) | RD(dest), ctx);
emit(cb_opc | WDISP10(off << 2) | RS1(dst) | RS2(src), ctx);
emit(cb_opc | IMMED | WDISP10(off << 2) | RS1(dst) | S5(imm), ctx);
#define emit_write_y(REG, CTX) emit(WR_Y | IMMED | RS1(REG) | S13(0), CTX)
emit(SUBCC | RS1(R1) | RS2(R2) | RD(G0), CTX)
emit(SUBCC | IMMED | RS1(R1) | S13(IMM) | RD(G0), CTX)
emit(ANDCC | RS1(R1) | RS2(R2) | RD(G0), CTX)
emit(ANDCC | IMMED | RS1(R1) | S13(IMM) | RD(G0), CTX)
emit(SAVE | IMMED | RS1(SP) | S13(-stack_needed) | RD(SP), ctx);
emit(ST32 | IMMED | RS1(SP) | S13(off) | RD(G0), ctx);
emit(ADD | IMMED | RS1(FP) | S13(STACK_BIAS) | RD(vfp), ctx);
emit(JMPL | IMMED | RS1(I7) | S13(8) | RD(G0), ctx);
emit(RESTORE | RS1(bpf2sparc[BPF_REG_0]) | RS2(G0) | RD(O0), ctx);
emit(LD32 | IMMED | RS1(bpf_array) | S13(off) | RD(tmp), ctx);
emit(LD32 | IMMED | RS1(SP) | S13(off) | RD(tmp), ctx);
emit(ST32 | IMMED | RS1(SP) | S13(off) | RD(tmp), ctx);
emit(LD64 | IMMED | RS1(tmp) | S13(off) | RD(tmp), ctx);
emit(LD64 | IMMED | RS1(tmp) | S13(off) | RD(tmp), ctx);
emit(JMPL | IMMED | RS1(tmp) | S13(off) | RD(G0), ctx);
emit(SUB | RS1(0) | RS2(dst) | RD(dst), ctx);