arch/mips/kernel/traps.c

732

int rs = (opcode & RS) >> 21;

arch/mips/mm/uasm-micromips.c

101

[insn_sll] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sll32_op), RT | RS | RD},

arch/mips/mm/uasm-micromips.c

102

[insn_sllv] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sllv32_op), RT | RS | RD},

arch/mips/mm/uasm-micromips.c

103

[insn_slt] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_slt_op), RT | RS | RD},

arch/mips/mm/uasm-micromips.c

104

[insn_sltiu] = {M(mm_sltiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},

arch/mips/mm/uasm-micromips.c

105

[insn_sltu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sltu_op), RT | RS | RD},

arch/mips/mm/uasm-micromips.c

106

[insn_sra] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD},

arch/mips/mm/uasm-micromips.c

107

[insn_srav] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srav_op), RT | RS | RD},

arch/mips/mm/uasm-micromips.c

108

[insn_srl] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srl32_op), RT | RS | RD},

arch/mips/mm/uasm-micromips.c

109

[insn_srlv] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srlv32_op), RT | RS | RD},

arch/mips/mm/uasm-micromips.c

110

[insn_rotr] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD},

arch/mips/mm/uasm-micromips.c

111

[insn_subu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_subu32_op), RT | RS | RD},

arch/mips/mm/uasm-micromips.c

112

[insn_sw] = {M(mm_sw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},

arch/mips/mm/uasm-micromips.c

113

[insn_sync] = {M(mm_pool32a_op, 0, 0, 0, mm_sync_op, mm_pool32axf_op), RS},

arch/mips/mm/uasm-micromips.c

119

[insn_wsbh] = {M(mm_pool32a_op, 0, 0, 0, mm_wsbh_op, mm_pool32axf_op), RT | RS},

arch/mips/mm/uasm-micromips.c

120

[insn_xor] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_xor32_op), RT | RS | RD},

arch/mips/mm/uasm-micromips.c

121

[insn_xori] = {M(mm_xori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM},

arch/mips/mm/uasm-micromips.c

171

if (ip->fields & RS) {

arch/mips/mm/uasm-micromips.c

43

[insn_addu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD},

arch/mips/mm/uasm-micromips.c

44

[insn_addiu] = {M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},

arch/mips/mm/uasm-micromips.c

45

[insn_and] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD},

arch/mips/mm/uasm-micromips.c

46

[insn_andi] = {M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM},

arch/mips/mm/uasm-micromips.c

47

[insn_beq] = {M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM},

arch/mips/mm/uasm-micromips.c

49

[insn_bgez] = {M(mm_pool32i_op, mm_bgez_op, 0, 0, 0, 0), RS | BIMM},

arch/mips/mm/uasm-micromips.c

51

[insn_bltz] = {M(mm_pool32i_op, mm_bltz_op, 0, 0, 0, 0), RS | BIMM},

arch/mips/mm/uasm-micromips.c

53

[insn_bne] = {M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM},

arch/mips/mm/uasm-micromips.c

54

[insn_cache] = {M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM},

arch/mips/mm/uasm-micromips.c

55

[insn_cfc1] = {M(mm_pool32f_op, 0, 0, 0, mm_cfc1_op, mm_32f_73_op), RT | RS},

arch/mips/mm/uasm-micromips.c

57

[insn_ctc1] = {M(mm_pool32f_op, 0, 0, 0, mm_ctc1_op, mm_32f_73_op), RT | RS},

arch/mips/mm/uasm-micromips.c

61

[insn_di] = {M(mm_pool32a_op, 0, 0, 0, mm_di_op, mm_pool32axf_op), RS},

arch/mips/mm/uasm-micromips.c

62

[insn_divu] = {M(mm_pool32a_op, 0, 0, 0, mm_divu_op, mm_pool32axf_op), RT | RS},

arch/mips/mm/uasm-micromips.c

74

[insn_ins] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_ins_op), RT | RS | RD | RE},

arch/mips/mm/uasm-micromips.c

75

[insn_ext] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_ext_op), RT | RS | RD | RE},

arch/mips/mm/uasm-micromips.c

78

[insn_jalr] = {M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RT | RS},

arch/mips/mm/uasm-micromips.c

79

[insn_jr] = {M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RS},

arch/mips/mm/uasm-micromips.c

80

[insn_lb] = {M(mm_lb32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},

arch/mips/mm/uasm-micromips.c

82

[insn_lh] = {M(mm_lh32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},

arch/mips/mm/uasm-micromips.c

83

[insn_ll] = {M(mm_pool32c_op, 0, 0, (mm_ll_func << 1), 0, 0), RS | RT | SIMM},

arch/mips/mm/uasm-micromips.c

85

[insn_lui] = {M(mm_pool32i_op, mm_lui_op, 0, 0, 0, 0), RS | SIMM},

arch/mips/mm/uasm-micromips.c

86

[insn_lw] = {M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},

arch/mips/mm/uasm-micromips.c

87

[insn_mfc0] = {M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD},

arch/mips/mm/uasm-micromips.c

88

[insn_mfhi] = {M(mm_pool32a_op, 0, 0, 0, mm_mfhi32_op, mm_pool32axf_op), RS},

arch/mips/mm/uasm-micromips.c

89

[insn_mflo] = {M(mm_pool32a_op, 0, 0, 0, mm_mflo32_op, mm_pool32axf_op), RS},

arch/mips/mm/uasm-micromips.c

90

[insn_mtc0] = {M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD},

arch/mips/mm/uasm-micromips.c

91

[insn_mthi] = {M(mm_pool32a_op, 0, 0, 0, mm_mthi32_op, mm_pool32axf_op), RS},

arch/mips/mm/uasm-micromips.c

92

[insn_mtlo] = {M(mm_pool32a_op, 0, 0, 0, mm_mtlo32_op, mm_pool32axf_op), RS},

arch/mips/mm/uasm-micromips.c

93

[insn_mul] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_mul_op), RT | RS | RD},

arch/mips/mm/uasm-micromips.c

94

[insn_or] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD},

arch/mips/mm/uasm-micromips.c

95

[insn_ori] = {M(mm_ori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM},

arch/mips/mm/uasm-micromips.c

96

[insn_pref] = {M(mm_pool32c_op, 0, 0, (mm_pref_func << 1), 0, 0), RT | RS | SIMM},

arch/mips/mm/uasm-micromips.c

98

[insn_sc] = {M(mm_pool32c_op, 0, 0, (mm_sc_func << 1), 0, 0), RT | RS | SIMM},

arch/mips/mm/uasm-mips.c

101

[insn_dsllv] = {M(spec_op, 0, 0, 0, 0, dsllv_op), RS | RT | RD},

arch/mips/mm/uasm-mips.c

104

[insn_dsrav] = {M(spec_op, 0, 0, 0, 0, dsrav_op), RS | RT | RD},

arch/mips/mm/uasm-mips.c

107

[insn_dsrlv] = {M(spec_op, 0, 0, 0, 0, dsrlv_op), RS | RT | RD},

arch/mips/mm/uasm-mips.c

108

[insn_dsubu] = {M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD},

arch/mips/mm/uasm-mips.c

110

[insn_ext] = {M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE},

arch/mips/mm/uasm-mips.c

111

[insn_ins] = {M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE},

arch/mips/mm/uasm-mips.c

114

[insn_jalr] = {M(spec_op, 0, 0, 0, 0, jalr_op), RS | RD},

arch/mips/mm/uasm-mips.c

116

[insn_jr] = {M(spec_op, 0, 0, 0, 0, jr_op), RS},

arch/mips/mm/uasm-mips.c

118

[insn_jr] = {M(spec_op, 0, 0, 0, 0, jalr_op), RS},

arch/mips/mm/uasm-mips.c

120

[insn_lb] = {M(lb_op, 0, 0, 0, 0, 0), RS | RT | SIMM},

arch/mips/mm/uasm-mips.c

121

[insn_lbu] = {M(lbu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},

arch/mips/mm/uasm-mips.c

122

[insn_ld] = {M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM},

arch/mips/mm/uasm-mips.c

123

[insn_lddir] = {M(lwc2_op, 0, 0, 0, lddir_op, mult_op), RS | RT | RD},

arch/mips/mm/uasm-mips.c

124

[insn_ldpte] = {M(lwc2_op, 0, 0, 0, ldpte_op, mult_op), RS | RD},

arch/mips/mm/uasm-mips.c

125

[insn_ldx] = {M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD},

arch/mips/mm/uasm-mips.c

126

[insn_lh] = {M(lh_op, 0, 0, 0, 0, 0), RS | RT | SIMM},

arch/mips/mm/uasm-mips.c

127

[insn_lhu] = {M(lhu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},

arch/mips/mm/uasm-mips.c

129

[insn_ll] = {M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM},

arch/mips/mm/uasm-mips.c

130

[insn_lld] = {M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM},

arch/mips/mm/uasm-mips.c

132

[insn_ll] = {M6(spec3_op, 0, 0, 0, ll6_op), RS | RT | SIMM9},

arch/mips/mm/uasm-mips.c

133

[insn_lld] = {M6(spec3_op, 0, 0, 0, lld6_op), RS | RT | SIMM9},

arch/mips/mm/uasm-mips.c

136

[insn_lw] = {M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM},

arch/mips/mm/uasm-mips.c

137

[insn_lwu] = {M(lwu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},

arch/mips/mm/uasm-mips.c

138

[insn_lwx] = {M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD},

arch/mips/mm/uasm-mips.c

144

RS | RT | RD},

arch/mips/mm/uasm-mips.c

145

[insn_movn] = {M(spec_op, 0, 0, 0, 0, movn_op), RS | RT | RD},

arch/mips/mm/uasm-mips.c

146

[insn_movz] = {M(spec_op, 0, 0, 0, 0, movz_op), RS | RT | RD},

arch/mips/mm/uasm-mips.c

149

[insn_mthi] = {M(spec_op, 0, 0, 0, 0, mthi_op), RS},

arch/mips/mm/uasm-mips.c

150

[insn_mtlo] = {M(spec_op, 0, 0, 0, 0, mtlo_op), RS},

arch/mips/mm/uasm-mips.c

152

RS | RT | RD},

arch/mips/mm/uasm-mips.c

154

RS | RT | RD},

arch/mips/mm/uasm-mips.c

156

[insn_mul] = {M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD},

arch/mips/mm/uasm-mips.c

158

[insn_mul] = {M(spec_op, 0, 0, 0, mult_mul_op, mult_op), RS | RT | RD},

arch/mips/mm/uasm-mips.c

160

[insn_multu] = {M(spec_op, 0, 0, 0, 0, multu_op), RS | RT},

arch/mips/mm/uasm-mips.c

161

[insn_nor] = {M(spec_op, 0, 0, 0, 0, nor_op), RS | RT | RD},

arch/mips/mm/uasm-mips.c

162

[insn_or] = {M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD},

arch/mips/mm/uasm-mips.c

163

[insn_ori] = {M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM},

arch/mips/mm/uasm-mips.c

165

[insn_pref] = {M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM},

arch/mips/mm/uasm-mips.c

167

[insn_pref] = {M6(spec3_op, 0, 0, 0, pref6_op), RS | RT | SIMM9},

arch/mips/mm/uasm-mips.c

171

[insn_sb] = {M(sb_op, 0, 0, 0, 0, 0), RS | RT | SIMM},

arch/mips/mm/uasm-mips.c

173

[insn_sc] = {M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM},

arch/mips/mm/uasm-mips.c

174

[insn_scd] = {M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM},

arch/mips/mm/uasm-mips.c

176

[insn_sc] = {M6(spec3_op, 0, 0, 0, sc6_op), RS | RT | SIMM9},

arch/mips/mm/uasm-mips.c

177

[insn_scd] = {M6(spec3_op, 0, 0, 0, scd6_op), RS | RT | SIMM9},

arch/mips/mm/uasm-mips.c

179

[insn_sd] = {M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM},

arch/mips/mm/uasm-mips.c

180

[insn_seleqz] = {M(spec_op, 0, 0, 0, 0, seleqz_op), RS | RT | RD},

arch/mips/mm/uasm-mips.c

181

[insn_selnez] = {M(spec_op, 0, 0, 0, 0, selnez_op), RS | RT | RD},

arch/mips/mm/uasm-mips.c

182

[insn_sh] = {M(sh_op, 0, 0, 0, 0, 0), RS | RT | SIMM},

arch/mips/mm/uasm-mips.c

184

[insn_sllv] = {M(spec_op, 0, 0, 0, 0, sllv_op), RS | RT | RD},

arch/mips/mm/uasm-mips.c

185

[insn_slt] = {M(spec_op, 0, 0, 0, 0, slt_op), RS | RT | RD},

arch/mips/mm/uasm-mips.c

186

[insn_slti] = {M(slti_op, 0, 0, 0, 0, 0), RS | RT | SIMM},

arch/mips/mm/uasm-mips.c

187

[insn_sltiu] = {M(sltiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},

arch/mips/mm/uasm-mips.c

188

[insn_sltu] = {M(spec_op, 0, 0, 0, 0, sltu_op), RS | RT | RD},

arch/mips/mm/uasm-mips.c

190

[insn_srav] = {M(spec_op, 0, 0, 0, 0, srav_op), RS | RT | RD},

arch/mips/mm/uasm-mips.c

192

[insn_srlv] = {M(spec_op, 0, 0, 0, 0, srlv_op), RS | RT | RD},

arch/mips/mm/uasm-mips.c

193

[insn_subu] = {M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD},

arch/mips/mm/uasm-mips.c

194

[insn_sw] = {M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM},

arch/mips/mm/uasm-mips.c

203

[insn_xor] = {M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD},

arch/mips/mm/uasm-mips.c

204

[insn_xori] = {M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM},

arch/mips/mm/uasm-mips.c

205

[insn_yield] = {M(spec3_op, 0, 0, 0, 0, yield_op), RS | RD},

arch/mips/mm/uasm-mips.c

247

if (ip->fields & RS)

arch/mips/mm/uasm-mips.c

51

[insn_addiu] = {M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},

arch/mips/mm/uasm-mips.c

52

[insn_addu] = {M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD},

arch/mips/mm/uasm-mips.c

53

[insn_and] = {M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD},

arch/mips/mm/uasm-mips.c

54

[insn_andi] = {M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM},

arch/mips/mm/uasm-mips.c

55

[insn_bbit0] = {M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM},

arch/mips/mm/uasm-mips.c

56

[insn_bbit1] = {M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM},

arch/mips/mm/uasm-mips.c

57

[insn_beq] = {M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM},

arch/mips/mm/uasm-mips.c

58

[insn_beql] = {M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM},

arch/mips/mm/uasm-mips.c

59

[insn_bgez] = {M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM},

arch/mips/mm/uasm-mips.c

60

[insn_bgezl] = {M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM},

arch/mips/mm/uasm-mips.c

61

[insn_bgtz] = {M(bgtz_op, 0, 0, 0, 0, 0), RS | BIMM},

arch/mips/mm/uasm-mips.c

62

[insn_blez] = {M(blez_op, 0, 0, 0, 0, 0), RS | BIMM},

arch/mips/mm/uasm-mips.c

63

[insn_bltz] = {M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM},

arch/mips/mm/uasm-mips.c

64

[insn_bltzl] = {M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM},

arch/mips/mm/uasm-mips.c

65

[insn_bne] = {M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM},

arch/mips/mm/uasm-mips.c

68

[insn_cache] = {M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM},

arch/mips/mm/uasm-mips.c

70

[insn_cache] = {M6(spec3_op, 0, 0, 0, cache6_op), RS | RT | SIMM9},

arch/mips/mm/uasm-mips.c

76

[insn_daddiu] = {M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},

arch/mips/mm/uasm-mips.c

77

[insn_daddu] = {M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD},

arch/mips/mm/uasm-mips.c

78

[insn_ddivu] = {M(spec_op, 0, 0, 0, 0, ddivu_op), RS | RT},

arch/mips/mm/uasm-mips.c

80

RS | RT | RD},

arch/mips/mm/uasm-mips.c

82

[insn_dins] = {M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE},

arch/mips/mm/uasm-mips.c

83

[insn_dinsm] = {M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE},

arch/mips/mm/uasm-mips.c

84

[insn_dinsu] = {M(spec3_op, 0, 0, 0, 0, dinsu_op), RS | RT | RD | RE},

arch/mips/mm/uasm-mips.c

85

[insn_divu] = {M(spec_op, 0, 0, 0, 0, divu_op), RS | RT},

arch/mips/mm/uasm-mips.c

87

RS | RT | RD},

arch/mips/mm/uasm-mips.c

90

RS | RT | RD},

arch/mips/mm/uasm-mips.c

92

[insn_dmultu] = {M(spec_op, 0, 0, 0, 0, dmultu_op), RS | RT},

arch/mips/mm/uasm-mips.c

94

RS | RT | RD},

arch/powerpc/include/asm/asm-compat.h

23

#define PPC_MTOCRF(FXM, RS) MTOCRF((FXM), RS)

arch/powerpc/include/asm/ppc_asm.h

470

#define MTOCRF(FXM, RS) \

arch/powerpc/include/asm/ppc_asm.h

472

mtcrf (FXM), RS; \

arch/powerpc/include/asm/ppc_asm.h

474

mtocrf (FXM), RS; \

arch/powerpc/platforms/powermac/time.c

54

#define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */

arch/powerpc/platforms/powermac/time.c

55

#define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */

arch/powerpc/platforms/powermac/time.c

56

#define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */

arch/powerpc/platforms/powermac/time.c

57

#define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */

arch/powerpc/platforms/powermac/time.c

58

#define ACR (11*RS) /* Auxiliary control register */

arch/powerpc/platforms/powermac/time.c

59

#define IFR (13*RS) /* Interrupt flag register */

arch/powerpc/xmon/ppc-opc.c

3259

{"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3262

{"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},

arch/powerpc/xmon/ppc-opc.c

3264

{"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3265

{"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}},

arch/powerpc/xmon/ppc-opc.c

3267

{"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}},

arch/powerpc/xmon/ppc-opc.c

3268

{"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},

arch/powerpc/xmon/ppc-opc.c

3270

{"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}},

arch/powerpc/xmon/ppc-opc.c

3272

{"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}},

arch/powerpc/xmon/ppc-opc.c

3273

{"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}},

arch/powerpc/xmon/ppc-opc.c

3275

{"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}},

arch/powerpc/xmon/ppc-opc.c

3276

{"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}},

arch/powerpc/xmon/ppc-opc.c

3279

{"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}},

arch/powerpc/xmon/ppc-opc.c

3280

{"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}},

arch/powerpc/xmon/ppc-opc.c

3282

{"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3285

{"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3286

{"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3287

{"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3288

{"evmr", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},

arch/powerpc/xmon/ppc-opc.c

3289

{"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3290

{"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3291

{"evnot", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},

arch/powerpc/xmon/ppc-opc.c

3293

{"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3294

{"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3295

{"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3296

{"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3297

{"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3298

{"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},

arch/powerpc/xmon/ppc-opc.c

3299

{"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},

arch/powerpc/xmon/ppc-opc.c

3300

{"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3301

{"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},

arch/powerpc/xmon/ppc-opc.c

3302

{"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3303

{"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}},

arch/powerpc/xmon/ppc-opc.c

3304

{"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},

arch/powerpc/xmon/ppc-opc.c

3305

{"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}},

arch/powerpc/xmon/ppc-opc.c

3306

{"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3307

{"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3308

{"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3309

{"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3327

{"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}},

arch/powerpc/xmon/ppc-opc.c

3329

{"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3331

{"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3333

{"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}},

arch/powerpc/xmon/ppc-opc.c

3335

{"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}},

arch/powerpc/xmon/ppc-opc.c

3336

{"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}},

arch/powerpc/xmon/ppc-opc.c

3339

{"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3340

{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3348

{"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3349

{"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3350

{"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3351

{"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3352

{"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3353

{"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3354

{"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3355

{"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3356

{"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3358

{"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3363

{"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3364

{"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3366

{"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},

arch/powerpc/xmon/ppc-opc.c

3368

{"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},

arch/powerpc/xmon/ppc-opc.c

3369

{"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},

arch/powerpc/xmon/ppc-opc.c

3372

{"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3373

{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3380

{"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3381

{"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3382

{"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3383

{"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3384

{"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3385

{"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3386

{"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3387

{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3388

{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3389

{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3391

{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3395

{"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3396

{"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3397

{"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3398

{"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3399

{"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}},

arch/powerpc/xmon/ppc-opc.c

3400

{"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}},

arch/powerpc/xmon/ppc-opc.c

3401

{"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}},

arch/powerpc/xmon/ppc-opc.c

3402

{"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3403

{"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3404

{"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3405

{"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3409

{"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3410

{"efdcfui", VX (4, 752), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3411

{"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3412

{"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3413

{"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3414

{"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3415

{"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3416

{"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3417

{"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3418

{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3420

{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

3424

{"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3426

{"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},

arch/powerpc/xmon/ppc-opc.c

3427

{"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3429

{"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},

arch/powerpc/xmon/ppc-opc.c

3430

{"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3432

{"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},

arch/powerpc/xmon/ppc-opc.c

3434

{"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3436

{"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},

arch/powerpc/xmon/ppc-opc.c

3439

{"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3442

{"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},

arch/powerpc/xmon/ppc-opc.c

3443

{"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3445

{"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},

arch/powerpc/xmon/ppc-opc.c

3447

{"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3449

{"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},

arch/powerpc/xmon/ppc-opc.c

3450

{"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3451

{"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},

arch/powerpc/xmon/ppc-opc.c

3452

{"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3453

{"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},

arch/powerpc/xmon/ppc-opc.c

3455

{"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3457

{"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},

arch/powerpc/xmon/ppc-opc.c

3458

{"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3459

{"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},

arch/powerpc/xmon/ppc-opc.c

3460

{"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3461

{"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},

arch/powerpc/xmon/ppc-opc.c

3462

{"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3463

{"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},

arch/powerpc/xmon/ppc-opc.c

3464

{"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3465

{"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},

arch/powerpc/xmon/ppc-opc.c

3466

{"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3467

{"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},

arch/powerpc/xmon/ppc-opc.c

3468

{"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3469

{"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},

arch/powerpc/xmon/ppc-opc.c

3470

{"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3471

{"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},

arch/powerpc/xmon/ppc-opc.c

3472

{"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3473

{"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},

arch/powerpc/xmon/ppc-opc.c

3518

{"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3524

{"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3526

{"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3527

{"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3529

{"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3530

{"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3532

{"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3533

{"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3538

{"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3539

{"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3540

{"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3541

{"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3542

{"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3543

{"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3544

{"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3545

{"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3555

{"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3557

{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3559

{"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3561

{"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3563

{"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3564

{"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3566

{"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3568

{"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3569

{"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3574

{"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3575

{"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3576

{"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3577

{"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3578

{"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3579

{"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3580

{"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3581

{"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3582

{"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3599

{"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}},

arch/powerpc/xmon/ppc-opc.c

3601

{"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}},

arch/powerpc/xmon/ppc-opc.c

3602

{"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}},

arch/powerpc/xmon/ppc-opc.c

3603

{"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}},

arch/powerpc/xmon/ppc-opc.c

3604

{"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}},

arch/powerpc/xmon/ppc-opc.c

3606

{"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3611

{"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3613

{"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}},

arch/powerpc/xmon/ppc-opc.c

3614

{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}},

arch/powerpc/xmon/ppc-opc.c

3615

{"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}},

arch/powerpc/xmon/ppc-opc.c

3616

{"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}},

arch/powerpc/xmon/ppc-opc.c

3625

{"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3627

{"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3629

{"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3630

{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3633

{"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3637

{"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3638

{"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3641

{"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3642

{"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3644

{"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3645

{"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3646

{"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3649

{"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3650

{"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3651

{"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3652

{"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3653

{"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3654

{"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3656

{"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3658

{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3665

{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3667

{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3670

{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3672

{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3674

{"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3675

{"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3678

{"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3680

{"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3689

{"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3691

{"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3692

{"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3696

{"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3697

{"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3698

{"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3699

{"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3700

{"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3701

{"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3702

{"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3705

{"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3706

{"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3707

{"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3708

{"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3709

{"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3710

{"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3711

{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3713

{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3719

{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3720

{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3723

{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3725

{"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3727

{"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

3728

{"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4586

{"rlwimi", M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4587

{"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4589

{"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4590

{"rlimi.", M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4592

{"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},

arch/powerpc/xmon/ppc-opc.c

4593

{"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}},

arch/powerpc/xmon/ppc-opc.c

4594

{"rlwinm", M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4595

{"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4596

{"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},

arch/powerpc/xmon/ppc-opc.c

4597

{"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}},

arch/powerpc/xmon/ppc-opc.c

4598

{"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4599

{"rlinm.", M(21,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4601

{"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4602

{"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4604

{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4605

{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4606

{"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4607

{"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4608

{"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4609

{"rlnm.", M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},

arch/powerpc/xmon/ppc-opc.c

4612

{"ori", OP(24), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},

arch/powerpc/xmon/ppc-opc.c

4613

{"oril", OP(24), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},

arch/powerpc/xmon/ppc-opc.c

4615

{"oris", OP(25), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},

arch/powerpc/xmon/ppc-opc.c

4616

{"oriu", OP(25), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},

arch/powerpc/xmon/ppc-opc.c

4619

{"xori", OP(26), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},

arch/powerpc/xmon/ppc-opc.c

4620

{"xoril", OP(26), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},

arch/powerpc/xmon/ppc-opc.c

4622

{"xoris", OP(27), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},

arch/powerpc/xmon/ppc-opc.c

4623

{"xoriu", OP(27), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},

arch/powerpc/xmon/ppc-opc.c

4625

{"andi.", OP(28), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},

arch/powerpc/xmon/ppc-opc.c

4626

{"andil.", OP(28), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},

arch/powerpc/xmon/ppc-opc.c

4628

{"andis.", OP(29), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},

arch/powerpc/xmon/ppc-opc.c

4629

{"andiu.", OP(29), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},

arch/powerpc/xmon/ppc-opc.c

4631

{"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}},

arch/powerpc/xmon/ppc-opc.c

4632

{"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}},

arch/powerpc/xmon/ppc-opc.c

4633

{"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},

arch/powerpc/xmon/ppc-opc.c

4634

{"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}},

arch/powerpc/xmon/ppc-opc.c

4635

{"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}},

arch/powerpc/xmon/ppc-opc.c

4636

{"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},

arch/powerpc/xmon/ppc-opc.c

4638

{"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},

arch/powerpc/xmon/ppc-opc.c

4639

{"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},

arch/powerpc/xmon/ppc-opc.c

4641

{"rldic", MD(30,2,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},

arch/powerpc/xmon/ppc-opc.c

4642

{"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},

arch/powerpc/xmon/ppc-opc.c

4644

{"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},

arch/powerpc/xmon/ppc-opc.c

4645

{"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},

arch/powerpc/xmon/ppc-opc.c

4647

{"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4648

{"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},

arch/powerpc/xmon/ppc-opc.c

4649

{"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4650

{"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},

arch/powerpc/xmon/ppc-opc.c

4652

{"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},

arch/powerpc/xmon/ppc-opc.c

4653

{"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},

arch/powerpc/xmon/ppc-opc.c

4737

{"slw", XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4738

{"sl", XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4739

{"slw.", XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4740

{"sl.", XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4742

{"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, 0, {RA, RS}},

arch/powerpc/xmon/ppc-opc.c

4743

{"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, 0, {RA, RS}},

arch/powerpc/xmon/ppc-opc.c

4744

{"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, 0, {RA, RS}},

arch/powerpc/xmon/ppc-opc.c

4745

{"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, 0, {RA, RS}},

arch/powerpc/xmon/ppc-opc.c

4747

{"sld", XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4748

{"sld.", XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4750

{"and", XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4751

{"and.", XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4753

{"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4754

{"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4805

{"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, 0, {RA, RS}},

arch/powerpc/xmon/ppc-opc.c

4806

{"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, 0, {RA, RS}},

arch/powerpc/xmon/ppc-opc.c

4808

{"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4809

{"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4841

{"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4842

{"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4844

{"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, 0, {SR, RS}},

arch/powerpc/xmon/ppc-opc.c

4870

{"mtsrdin", X(31,114), XRA_MASK, PPC64, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4882

{"popcntb", X(31,122), XRB_MASK, POWER5, 0, {RA, RS}},

arch/powerpc/xmon/ppc-opc.c

4884

{"not", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RBS}},

arch/powerpc/xmon/ppc-opc.c

4885

{"nor", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4886

{"not.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RBS}},

arch/powerpc/xmon/ppc-opc.c

4887

{"nor.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4893

{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

4915

{"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

4916

{"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, 0, {FXM, RS}},

arch/powerpc/xmon/ppc-opc.c

4917

{"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, 0, {FXM, RS}},

arch/powerpc/xmon/ppc-opc.c

4919

{"mtmsr", X(31,146), XRLARB_MASK, COM, 0, {RS, A_L}},

arch/powerpc/xmon/ppc-opc.c

4926

{"stdx", X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4928

{"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4930

{"stwx", X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4931

{"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

4933

{"slq", XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4934

{"slq.", XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4936

{"sle", XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4937

{"sle.", XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

4939

{"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}},

arch/powerpc/xmon/ppc-opc.c

4941

{"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4943

{"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4957

{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, 0, {RS, A_L}},

arch/powerpc/xmon/ppc-opc.c

4964

{"stdux", X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}},

arch/powerpc/xmon/ppc-opc.c

4969

{"stwux", X(31,183), X_MASK, PPCCOM, 0, {RS, RAS, RB}},

arch/powerpc/xmon/ppc-opc.c

4970

{"stux", X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

4972

{"sliq", XRC(31,184,0), X_MASK, M601, 0, {RA, RS, SH}},

arch/powerpc/xmon/ppc-opc.c

4973

{"sliq.", XRC(31,184,1), X_MASK, M601, 0, {RA, RS, SH}},

arch/powerpc/xmon/ppc-opc.c

4975

{"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}},

arch/powerpc/xmon/ppc-opc.c

4996

{"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}},

arch/powerpc/xmon/ppc-opc.c

5001

{"eratwe", X(31,211), X_MASK, PPCA2, 0, {RS, RA, WS}},

arch/powerpc/xmon/ppc-opc.c

5005

{"stdcx.", XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5007

{"stbx", X(31,215), X_MASK, COM, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5009

{"sllq", XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5010

{"sllq.", XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5012

{"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5013

{"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5015

{"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5044

{"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5045

{"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5056

{"stbux", X(31,247), X_MASK, COM, 0, {RS, RAS, RB}},

arch/powerpc/xmon/ppc-opc.c

5058

{"slliq", XRC(31,248,0), X_MASK, M601, 0, {RA, RS, SH}},

arch/powerpc/xmon/ppc-opc.c

5059

{"slliq.", XRC(31,248,1), X_MASK, M601, 0, {RA, RS, SH}},

arch/powerpc/xmon/ppc-opc.c

5061

{"bpermd", X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5065

{"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}},

arch/powerpc/xmon/ppc-opc.c

5066

{"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, 0, {RS, RA}},

arch/powerpc/xmon/ppc-opc.c

5109

{"cdtbcd", X(31,282), XRB_MASK, POWER6, 0, {RA, RS}},

arch/powerpc/xmon/ppc-opc.c

5111

{"eqv", XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5112

{"eqv.", XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5116

{"mfdcrux", X(31,291), X_MASK, PPC464, 0, {RS, RA}},

arch/powerpc/xmon/ppc-opc.c

5125

{"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}},

arch/powerpc/xmon/ppc-opc.c

5126

{"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}},

arch/powerpc/xmon/ppc-opc.c

5138

{"cbcdtd", X(31,314), XRB_MASK, POWER6, 0, {RA, RS}},

arch/powerpc/xmon/ppc-opc.c

5140

{"xor", XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5141

{"xor.", XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5380

{"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5426

{"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},

arch/powerpc/xmon/ppc-opc.c

5428

{"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}},

arch/powerpc/xmon/ppc-opc.c

5429

{"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, 0, {RA, RS}},

arch/powerpc/xmon/ppc-opc.c

5446

{"slbmte", X(31,402), XRA_MASK, PPC64, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5450

{"pbt.", XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5452

{"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5453

{"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5455

{"sthx", X(31,407), X_MASK, COM, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5457

{"orc", XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5458

{"orc.", XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5460

{"sthepx", X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5462

{"mtdcrux", X(31,419), X_MASK, PPC464, 0, {RA, RS}},

arch/powerpc/xmon/ppc-opc.c

5483

{"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}},

arch/powerpc/xmon/ppc-opc.c

5494

{"mr", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RBS}},

arch/powerpc/xmon/ppc-opc.c

5495

{"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5496

{"mr.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RBS}},

arch/powerpc/xmon/ppc-opc.c

5497

{"or.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5499

{"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5500

{"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5501

{"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5502

{"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5503

{"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5504

{"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5505

{"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5506

{"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5507

{"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5508

{"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5509

{"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5510

{"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5511

{"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5512

{"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5513

{"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5514

{"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5515

{"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5516

{"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5517

{"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5518

{"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5519

{"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5520

{"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5521

{"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5522

{"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5523

{"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5524

{"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5525

{"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5526

{"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5527

{"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5528

{"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5529

{"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5530

{"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5531

{"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5532

{"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5533

{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}},

arch/powerpc/xmon/ppc-opc.c

5534

{"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, 0, {SPR, RS}},

arch/powerpc/xmon/ppc-opc.c

5547

{"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}},

arch/powerpc/xmon/ppc-opc.c

5548

{"mttmr", X(31,494), X_MASK, PPCTMR|E6500, 0, {TMR, RS}},

arch/powerpc/xmon/ppc-opc.c

5550

{"slbieg", X(31,466), XRA_MASK, POWER9, 0, {RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5552

{"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5553

{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5554

{"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5555

{"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5556

{"mtdscr", XSPR(31,467, 17), XSPR_MASK, POWER6, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5557

{"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5558

{"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}},

arch/powerpc/xmon/ppc-opc.c

5559

{"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}},

arch/powerpc/xmon/ppc-opc.c

5560

{"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, TITAN, {RS}},

arch/powerpc/xmon/ppc-opc.c

5561

{"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, TITAN, {RS}},

arch/powerpc/xmon/ppc-opc.c

5562

{"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5563

{"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5564

{"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, TITAN, {RS}},

arch/powerpc/xmon/ppc-opc.c

5565

{"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5566

{"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5567

{"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5568

{"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5569

{"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5570

{"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5571

{"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5572

{"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5573

{"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5574

{"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5575

{"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5576

{"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5577

{"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5578

{"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5579

{"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5580

{"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5581

{"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5582

{"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5583

{"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5584

{"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5585

{"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5586

{"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5587

{"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5588

{"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5589

{"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5590

{"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5591

{"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5592

{"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5593

{"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5594

{"mtsprg", XSPR(31,467,256), XSPRG_MASK, PPC, 0, {SPRG, RS}},

arch/powerpc/xmon/ppc-opc.c

5595

{"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5596

{"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5597

{"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5598

{"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5599

{"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5600

{"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5601

{"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5602

{"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5603

{"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5604

{"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}},

arch/powerpc/xmon/ppc-opc.c

5605

{"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5606

{"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5607

{"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5608

{"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5609

{"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5610

{"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5611

{"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5612

{"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5613

{"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5614

{"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5615

{"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5616

{"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5617

{"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5618

{"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5619

{"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5620

{"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5621

{"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5622

{"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5623

{"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5624

{"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5625

{"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5626

{"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5627

{"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5628

{"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5629

{"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5630

{"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5631

{"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5632

{"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5633

{"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5634

{"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5635

{"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5636

{"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5637

{"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5638

{"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5639

{"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5640

{"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5641

{"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},

arch/powerpc/xmon/ppc-opc.c

5642

{"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5643

{"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},

arch/powerpc/xmon/ppc-opc.c

5644

{"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5645

{"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5646

{"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},

arch/powerpc/xmon/ppc-opc.c

5647

{"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},

arch/powerpc/xmon/ppc-opc.c

5648

{"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5649

{"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5650

{"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5651

{"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5652

{"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5653

{"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5654

{"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5655

{"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5656

{"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5657

{"mtppr", XSPR(31,467,896), XSPR_MASK, POWER7, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5658

{"mtppr32", XSPR(31,467,898), XSPR_MASK, POWER7, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5659

{"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

566

#define RT RS

arch/powerpc/xmon/ppc-opc.c

5660

{"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5661

{"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5662

{"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5663

{"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5664

{"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5665

{"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5666

{"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5667

{"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5668

{"mtrmmucr", XSPR(31,467,946), XSPR_MASK, TITAN, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5669

{"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5670

{"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5671

{"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5672

{"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5673

{"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5674

{"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5675

{"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5676

{"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5677

{"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5678

{"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5679

{"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

568

#define RD RS

arch/powerpc/xmon/ppc-opc.c

5680

{"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5681

{"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5682

{"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5683

{"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5684

{"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5685

{"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5686

{"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5687

{"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5688

{"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5689

{"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5690

{"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5691

{"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5692

{"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5693

{"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5694

{"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5695

{"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5696

{"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5697

{"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5698

{"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5699

{"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5700

{"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5701

{"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5702

{"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5703

{"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5704

{"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5705

{"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5706

{"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5707

{"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5708

{"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5709

{"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5710

{"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5711

{"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5712

{"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5713

{"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5714

{"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5715

{"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

5716

{"mtspr", X(31,467), X_MASK, COM, 0, {SPR, RS}},

arch/powerpc/xmon/ppc-opc.c

5720

{"nand", XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5721

{"nand.", XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

573

#define RSQ RS + 1

arch/powerpc/xmon/ppc-opc.c

5747

{"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},

arch/powerpc/xmon/ppc-opc.c

5749

{"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5787

{"srw", XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5788

{"sr", XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5789

{"srw.", XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5790

{"sr.", XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5792

{"rrib", XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5793

{"rrib.", XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5795

{"cnttzw", XRC(31,538,0), XRB_MASK, POWER9, 0, {RA, RS}},

arch/powerpc/xmon/ppc-opc.c

5796

{"cnttzw.", XRC(31,538,1), XRB_MASK, POWER9, 0, {RA, RS}},

arch/powerpc/xmon/ppc-opc.c

5798

{"srd", XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5799

{"srd.", XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5801

{"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5802

{"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5823

{"cnttzd", XRC(31,570,0), XRB_MASK, POWER9, 0, {RA, RS}},

arch/powerpc/xmon/ppc-opc.c

5824

{"cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, 0, {RA, RS}},

arch/powerpc/xmon/ppc-opc.c

5875

{"dclst", X(31,630), XRB_MASK, M601, 0, {RS, RA}},

arch/powerpc/xmon/ppc-opc.c

5879

{"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5880

{"stbdx", X(31,643), X_MASK, E500MC, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5901

{"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5903

{"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5904

{"stsx", X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5906

{"stwbrx", X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5907

{"stbrx", X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5911

{"srq", XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5912

{"srq.", XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5914

{"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5915

{"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5917

{"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5918

{"sthdx", X(31,675), X_MASK, E500MC, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5928

{"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5932

{"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}},

arch/powerpc/xmon/ppc-opc.c

5933

{"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}},

arch/powerpc/xmon/ppc-opc.c

5935

{"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5936

{"stwdx", X(31,707), X_MASK, E500MC, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5940

{"stwat", X(31,710), X_MASK, POWER9, 0, {RS, RA0, FC}},

arch/powerpc/xmon/ppc-opc.c

5958

{"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}},

arch/powerpc/xmon/ppc-opc.c

5959

{"stsi", X(31,725), X_MASK, PWRCOM, 0, {RS, RA0, NB}},

arch/powerpc/xmon/ppc-opc.c

5961

{"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

5965

{"srlq", XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5966

{"srlq.", XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5968

{"sreq", XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5969

{"sreq.", XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

5974

{"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

5978

{"stdat", X(31,742), X_MASK, POWER9, 0, {RS, RA0, FC}},

arch/powerpc/xmon/ppc-opc.c

6011

{"srliq", XRC(31,760,0), X_MASK, M601, 0, {RA, RS, SH}},

arch/powerpc/xmon/ppc-opc.c

6012

{"srliq.", XRC(31,760,1), X_MASK, M601, 0, {RA, RS, SH}},

arch/powerpc/xmon/ppc-opc.c

6047

{"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

6048

{"sra", XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

6049

{"sraw.", XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

6050

{"sra.", XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

6052

{"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

6053

{"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

6068

{"erativax", X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6076

{"srawi", XRC(31,824,0), X_MASK, PPCCOM, 0, {RA, RS, SH}},

arch/powerpc/xmon/ppc-opc.c

6077

{"srai", XRC(31,824,0), X_MASK, PWRCOM, 0, {RA, RS, SH}},

arch/powerpc/xmon/ppc-opc.c

6078

{"srawi.", XRC(31,824,1), X_MASK, PPCCOM, 0, {RA, RS, SH}},

arch/powerpc/xmon/ppc-opc.c

6079

{"srai.", XRC(31,824,1), X_MASK, PWRCOM, 0, {RA, RS, SH}},

arch/powerpc/xmon/ppc-opc.c

6081

{"sradi", XS(31,413,0), XS_MASK, PPC64, 0, {RA, RS, SH6}},

arch/powerpc/xmon/ppc-opc.c

6082

{"sradi.", XS(31,413,1), XS_MASK, PPC64, 0, {RA, RS, SH6}},

arch/powerpc/xmon/ppc-opc.c

6098

{"slbiag", X(31,850), XRARB_MASK, POWER9, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

6131

{"extswsli", XS(31,445,0), XS_MASK, POWER9, 0, {RA, RS, SH6}},

arch/powerpc/xmon/ppc-opc.c

6132

{"extswsli.", XS(31,445,1), XS_MASK, POWER9, 0, {RA, RS, SH6}},

arch/powerpc/xmon/ppc-opc.c

6155

{"stwcix", X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6157

{"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6162

{"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

6163

{"sraq.", XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

6165

{"srea", XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

6166

{"srea.", XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

6168

{"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, 0, {RA, RS}},

arch/powerpc/xmon/ppc-opc.c

6169

{"exts", XRC(31,922,0), XRB_MASK, PWRCOM, 0, {RA, RS}},

arch/powerpc/xmon/ppc-opc.c

6170

{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, 0, {RA, RS}},

arch/powerpc/xmon/ppc-opc.c

6171

{"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, 0, {RA, RS}},

arch/powerpc/xmon/ppc-opc.c

6197

{"sthcix", X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6199

{"icswepx", XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6200

{"icswepx.", XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}},

arch/powerpc/xmon/ppc-opc.c

6204

{"sraiq", XRC(31,952,0), X_MASK, M601, 0, {RA, RS, SH}},

arch/powerpc/xmon/ppc-opc.c

6205

{"sraiq.", XRC(31,952,1), X_MASK, M601, 0, {RA, RS, SH}},

arch/powerpc/xmon/ppc-opc.c

6207

{"extsb", XRC(31,954,0), XRB_MASK, PPC, 0, {RA, RS}},

arch/powerpc/xmon/ppc-opc.c

6208

{"extsb.", XRC(31,954,1), XRB_MASK, PPC, 0, {RA, RS}},

arch/powerpc/xmon/ppc-opc.c

6231

{"stbcix", X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6237

{"extsw", XRC(31,986,0), XRB_MASK, PPC64, 0, {RA, RS}},

arch/powerpc/xmon/ppc-opc.c

6238

{"extsw.", XRC(31,986,1), XRB_MASK, PPC64, 0, {RA, RS}},

arch/powerpc/xmon/ppc-opc.c

6261

{"stdcix", X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}},

arch/powerpc/xmon/ppc-opc.c

6293

{"stw", OP(36), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

6294

{"st", OP(36), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

6296

{"stwu", OP(37), OP_MASK, PPCCOM, PPCVLE, {RS, D, RAS}},

arch/powerpc/xmon/ppc-opc.c

6297

{"stu", OP(37), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

6299

{"stb", OP(38), OP_MASK, COM, PPCVLE, {RS, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

6301

{"stbu", OP(39), OP_MASK, COM, PPCVLE, {RS, D, RAS}},

arch/powerpc/xmon/ppc-opc.c

6311

{"sth", OP(44), OP_MASK, COM, PPCVLE, {RS, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

6313

{"sthu", OP(45), OP_MASK, COM, PPCVLE, {RS, D, RAS}},

arch/powerpc/xmon/ppc-opc.c

6318

{"stmw", OP(47), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

6319

{"stm", OP(47), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},

arch/powerpc/xmon/ppc-opc.c

6672

{"std", DSO(62,0), DS_MASK, PPC64, PPCVLE, {RS, DS, RA0}},

arch/powerpc/xmon/ppc-opc.c

6673

{"stdu", DSO(62,1), DS_MASK, PPC64, PPCVLE, {RS, DS, RAS}},

arch/powerpc/xmon/ppc-opc.c

7024

{"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},

arch/powerpc/xmon/ppc-opc.c

7025

{"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},

arch/powerpc/xmon/ppc-opc.c

7027

{"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},

arch/powerpc/xmon/ppc-opc.c

7028

{"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},

arch/powerpc/xmon/ppc-opc.c

7029

{"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},

arch/powerpc/xmon/ppc-opc.c

7030

{"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},

arch/powerpc/xmon/ppc-opc.c

7104

{"e_rlwimi", M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}},

arch/powerpc/xmon/ppc-opc.c

7153

{"e_slwi", EX(31,112), EX_MASK, PPCVLE, 0, {RA, RS, SH}},

arch/powerpc/xmon/ppc-opc.c

7154

{"e_slwi.", EX(31,113), EX_MASK, PPCVLE, 0, {RA, RS, SH}},

arch/powerpc/xmon/ppc-opc.c

7158

{"e_rlw", EX(31,560), EX_MASK, PPCVLE, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

7159

{"e_rlw.", EX(31,561), EX_MASK, PPCVLE, 0, {RA, RS, RB}},

arch/powerpc/xmon/ppc-opc.c

7164

{"e_rlwi", EX(31,624), EX_MASK, PPCVLE, 0, {RA, RS, SH}},

arch/powerpc/xmon/ppc-opc.c

7165

{"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, 0, {RA, RS, SH}},

arch/powerpc/xmon/ppc-opc.c

7172

{"mtmas1", XSPR(31,467,625), XSPR_MASK, PPCVLE, 0, {RS}},

arch/powerpc/xmon/ppc-opc.c

7174

{"e_srwi", EX(31,1136), EX_MASK, PPCVLE, 0, {RA, RS, SH}},

arch/powerpc/xmon/ppc-opc.c

7175

{"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, 0, {RA, RS, SH}},

drivers/edac/pnd2_edac.c

763

R(10), C(7), C(8), C(9), R(11), RS, R(12), R(13), R(14),

drivers/edac/pnd2_edac.c

773

R(10), C(7), C(8), C(9), R(11), RS, R(12), R(13), R(14),

drivers/edac/pnd2_edac.c

783

R(10), C(7), C(8), C(9), R(11), RS, R(12), R(13), R(14),

drivers/edac/pnd2_edac.c

793

R(10), C(7), C(8), C(9), R(11), RS, C(11), R(12), R(13),

drivers/edac/pnd2_edac.c

803

R(9), R(10), C(8), C(9), R(11), RS, R(12), R(13), R(14),

drivers/edac/pnd2_edac.c

813

R(9), R(10), C(8), C(9), R(11), RS, R(12), R(13), R(14),

drivers/edac/pnd2_edac.c

823

R(9), R(10), C(8), C(9), R(11), RS, R(12), R(13), R(14),

drivers/edac/pnd2_edac.c

833

R(9), R(10), C(8), C(9), R(11), RS, C(11), R(12), R(13),

drivers/edac/pnd2_edac.c

843

R(8), R(9), R(10), C(9), R(11), RS, R(12), R(13), R(14),

drivers/edac/pnd2_edac.c

853

R(8), R(9), R(10), C(9), R(11), RS, R(12), R(13), R(14),

drivers/edac/pnd2_edac.c

863

R(8), R(9), R(10), C(9), R(11), RS, R(12), R(13), R(14),

drivers/edac/pnd2_edac.c

873

R(8), R(9), R(10), C(9), R(11), RS, C(11), R(12), R(13),

drivers/edac/pnd2_edac.c

930

if (type == RS && (cr_drp0->rken0 + cr_drp0->rken1) == 1) {

drivers/edac/pnd2_edac.c

948

case RS:

drivers/macintosh/via-cuda.c

41

#define A RS /* A-side data */

drivers/macintosh/via-cuda.c

42

#define DIRB (2*RS) /* B-side direction (1=output) */

drivers/macintosh/via-cuda.c

43

#define DIRA (3*RS) /* A-side direction (1=output) */

drivers/macintosh/via-cuda.c

44

#define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */

drivers/macintosh/via-cuda.c

45

#define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */

drivers/macintosh/via-cuda.c

46

#define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */

drivers/macintosh/via-cuda.c

47

#define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */

drivers/macintosh/via-cuda.c

48

#define T2CL (8*RS) /* Timer 2 ctr/latch (low 8 bits) */

drivers/macintosh/via-cuda.c

49

#define T2CH (9*RS) /* Timer 2 counter (high 8 bits) */

drivers/macintosh/via-cuda.c

50

#define SR (10*RS) /* Shift register */

drivers/macintosh/via-cuda.c

51

#define ACR (11*RS) /* Auxiliary control register */

drivers/macintosh/via-cuda.c

52

#define PCR (12*RS) /* Peripheral control register */

drivers/macintosh/via-cuda.c

53

#define IFR (13*RS) /* Interrupt flag register */

drivers/macintosh/via-cuda.c

54

#define IER (14*RS) /* Interrupt enable register */

drivers/macintosh/via-cuda.c

55

#define ANH (15*RS) /* A-side data, no handshake */

drivers/macintosh/via-macii.c

42

#define A RS /* A-side data */

drivers/macintosh/via-macii.c

43

#define DIRB (2*RS) /* B-side direction (1=output) */

drivers/macintosh/via-macii.c

44

#define DIRA (3*RS) /* A-side direction (1=output) */

drivers/macintosh/via-macii.c

45

#define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */

drivers/macintosh/via-macii.c

46

#define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */

drivers/macintosh/via-macii.c

47

#define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */

drivers/macintosh/via-macii.c

48

#define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */

drivers/macintosh/via-macii.c

49

#define T2CL (8*RS) /* Timer 2 ctr/latch (low 8 bits) */

drivers/macintosh/via-macii.c

50

#define T2CH (9*RS) /* Timer 2 counter (high 8 bits) */

drivers/macintosh/via-macii.c

51

#define SR (10*RS) /* Shift register */

drivers/macintosh/via-macii.c

52

#define ACR (11*RS) /* Auxiliary control register */

drivers/macintosh/via-macii.c

53

#define PCR (12*RS) /* Peripheral control register */

drivers/macintosh/via-macii.c

54

#define IFR (13*RS) /* Interrupt flag register */

drivers/macintosh/via-macii.c

55

#define IER (14*RS) /* Interrupt enable register */

drivers/macintosh/via-macii.c

56

#define ANH (15*RS) /* A-side data, no handshake */

drivers/macintosh/via-pmu.c

85

#define A RS /* A-side data */

drivers/macintosh/via-pmu.c

86

#define DIRB (2*RS) /* B-side direction (1=output) */

drivers/macintosh/via-pmu.c

87

#define DIRA (3*RS) /* A-side direction (1=output) */

drivers/macintosh/via-pmu.c

88

#define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */

drivers/macintosh/via-pmu.c

89

#define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */

drivers/macintosh/via-pmu.c

90

#define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */

drivers/macintosh/via-pmu.c

91

#define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */

drivers/macintosh/via-pmu.c

92

#define T2CL (8*RS) /* Timer 2 ctr/latch (low 8 bits) */

drivers/macintosh/via-pmu.c

93

#define T2CH (9*RS) /* Timer 2 counter (high 8 bits) */

drivers/macintosh/via-pmu.c

94

#define SR (10*RS) /* Shift register */

drivers/macintosh/via-pmu.c

95

#define ACR (11*RS) /* Auxiliary control register */

drivers/macintosh/via-pmu.c

96

#define PCR (12*RS) /* Peripheral control register */

drivers/macintosh/via-pmu.c

97

#define IFR (13*RS) /* Interrupt flag register */

drivers/macintosh/via-pmu.c

98

#define IER (14*RS) /* Interrupt enable register */

drivers/macintosh/via-pmu.c

99

#define ANH (15*RS) /* A-side data, no handshake */

drivers/staging/fbtft/fb_agm1264k-fl.c

192

gpiod_set_value(par->RS, 0); /* RS->0 (command mode) */

drivers/staging/fbtft/fb_agm1264k-fl.c

355

gpiod_set_value(par->RS, 1); /* RS->1 (data mode) */

drivers/staging/fbtft/fb_agm1264k-fl.c

378

gpiod_set_value(par->RS, 1); /* RS->1 (data mode) */

tools/testing/selftests/powerpc/primitives/asm/asm-compat.h

23

#define PPC_MTOCRF(FXM, RS) MTOCRF((FXM), RS)

tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h

470

#define MTOCRF(FXM, RS) \

tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h

472

mtcrf (FXM), RS; \

tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h

474

mtocrf (FXM), RS; \