drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

482

act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

487

if (low == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE) &&

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

488

high == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI))

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

611

temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

202

value = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

468

act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

473

if (low == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE) &&

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

474

high == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI))

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

534

temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1047

queue_map = RREG32_SOC15(GC, GET_INST(GC, inst), mmSPI_CSQ_WF_ACTIVE_STATUS);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1137

if (!RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE))

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1140

low = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1141

high = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE_HI);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1163

uint32_t temp = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1185

if (!RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE))

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1188

low = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1189

high = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE_HI);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

493

act = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

498

if (low == RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE) &&

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

499

high == RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE_HI))

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

561

temp = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

971

(RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL) &

drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h

68

RREG32_SOC15(JPEG, inst_idx, mmUVD_DPG_LMA_DATA); \

drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h

93

RREG32_SOC15(JPEG, inst_idx, regUVD_DPG_LMA_DATA); \

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

141

RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA); \

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

87

RREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA); \

drivers/gpu/drm/amd/amdgpu/athub_v1_0.c

37

def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);

drivers/gpu/drm/amd/amdgpu/athub_v1_0.c

53

def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);

drivers/gpu/drm/amd/amdgpu/athub_v1_0.c

98

data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);

drivers/gpu/drm/amd/amdgpu/athub_v2_0.c

101

data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);

drivers/gpu/drm/amd/amdgpu/athub_v2_0.c

42

def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);

drivers/gpu/drm/amd/amdgpu/athub_v2_0.c

63

def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);

drivers/gpu/drm/amd/amdgpu/athub_v2_1.c

38

def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);

drivers/gpu/drm/amd/amdgpu/athub_v2_1.c

55

def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);

drivers/gpu/drm/amd/amdgpu/athub_v2_1.c

93

data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);

drivers/gpu/drm/amd/amdgpu/athub_v3_0.c

43

data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_0_1);

drivers/gpu/drm/amd/amdgpu/athub_v3_0.c

46

data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_3_0);

drivers/gpu/drm/amd/amdgpu/athub_v3_0.c

49

data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL);

drivers/gpu/drm/amd/amdgpu/athub_v4_1_0.c

36

data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL);

drivers/gpu/drm/amd/amdgpu/df_v1_7.c

109

tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);

drivers/gpu/drm/amd/amdgpu/df_v1_7.c

49

tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl);

drivers/gpu/drm/amd/amdgpu/df_v1_7.c

61

tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);

drivers/gpu/drm/amd/amdgpu/df_v1_7.c

88

tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);

drivers/gpu/drm/amd/amdgpu/df_v1_7.c

93

tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);

drivers/gpu/drm/amd/amdgpu/df_v3_6.c

227

tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DfGlobalCtrl);

drivers/gpu/drm/amd/amdgpu/df_v3_6.c

268

tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl);

drivers/gpu/drm/amd/amdgpu/df_v3_6.c

281

tmp = RREG32_SOC15(DF, 0, mmDF_GCM_AON0_DramMegaBaseAddress0);

drivers/gpu/drm/amd/amdgpu/df_v3_6.c

285

tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DramBaseAddress0);

drivers/gpu/drm/amd/amdgpu/df_v3_6.c

314

tmp = RREG32_SOC15(DF, 0,

drivers/gpu/drm/amd/amdgpu/df_v3_6.c

321

tmp = RREG32_SOC15(DF, 0,

drivers/gpu/drm/amd/amdgpu/df_v3_6.c

340

tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);

drivers/gpu/drm/amd/amdgpu/df_v3_6.c

645

hw_assert_msklo = RREG32_SOC15(DF, 0,

drivers/gpu/drm/amd/amdgpu/df_v3_6.c

647

hw_assert_mskhi = RREG32_SOC15(DF, 0,

drivers/gpu/drm/amd/amdgpu/df_v4_15.c

37

tmp = RREG32_SOC15(DF, 0, regNCSConfigurationRegister1);

drivers/gpu/drm/amd/amdgpu/df_v4_3.c

34

hw_assert_msklo = RREG32_SOC15(DF, 0,

drivers/gpu/drm/amd/amdgpu/df_v4_3.c

36

hw_assert_mskhi = RREG32_SOC15(DF, 0,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

10076

efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

10080

vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

10171

efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

10175

vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

3839

if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

3857

if (!(RREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

4482

return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

4495

*(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

4558

data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

4594

gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

4609

gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5088

data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5089

data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5304

tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5310

tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5328

tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5329

RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5331

tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5332

RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5471

u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5490

rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5525

tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5866

tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5873

tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5890

tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5896

tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5927

tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5933

tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5964

tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5970

tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6001

tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6007

tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6037

cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6038

bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6076

u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6091

if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6137

tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6143

tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6158

tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6215

tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6221

tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6236

tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6292

tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6298

tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6313

tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6449

tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6461

tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6667

tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6673

tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6688

tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6731

tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6737

tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6758

tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6780

tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6787

tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6795

tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6817

tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6826

tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6838

mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6927

tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6934

tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6963

tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6973

tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7000

mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7005

tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7010

tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7037

if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7040

if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7295

data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7299

if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7311

data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7315

if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7467

data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7471

data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7585

if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7600

tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7617

tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7638

tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7672

tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7676

tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7682

tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7860

rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7885

if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7896

if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7944

def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7959

def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7966

def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7974

def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7985

data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7992

data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

8012

def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

8023

def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

8038

def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

8045

def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

8069

def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

8083

def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

8098

def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

8104

def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

8128

def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

8135

def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

8142

def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

8149

def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

8361

u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

8559

wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

8560

wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9419

tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9429

tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9604

if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

1990

gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regCC_GC_SA_UNIT_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

1994

gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGC_USER_SA_UNIT_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2009

gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2013

gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2082

data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2127

uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) |

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2128

RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2149

tmp = RREG32_SOC15(GC, 0, regTA_CNTL2);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2261

u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2280

rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2378

tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2408

tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2427

tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2506

tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2512

tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2527

tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2550

tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2556

tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2571

tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2594

tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2601

tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2616

tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2646

tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2658

tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2671

tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2676

tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2701

tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2727

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2733

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2738

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2768

tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2780

tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2793

tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2799

tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2824

tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2850

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2856

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2861

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2886

tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2892

tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2919

tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2925

tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2938

tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2944

tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2985

tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3007

tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3029

tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3052

cp_status = RREG32_SOC15(GC, 0, regCP_STAT);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3063

bootload_status = RREG32_SOC15(GC, 0,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3066

bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3129

u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3136

if (RREG32_SOC15(GC, 0, regCP_STAT) == 0)

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3258

tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3270

tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3283

tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3288

tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3313

tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3339

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3345

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3350

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3476

tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3488

tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3501

tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3507

tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3532

tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3558

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3564

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3569

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3695

tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3706

tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3831

data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3854

data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3981

tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3987

tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4014

tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4020

tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4033

tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4039

tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4060

tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4407

if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4410

if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4691

tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4695

tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4708

gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4744

data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4748

data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4848

adev->gfx.imu_fw_version = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4952

if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS),

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4967

tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) &

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4988

val = RREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5018

tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5061

RREG32_SOC15(GC, 0, regCP_VMID_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5062

RREG32_SOC15(GC, 0, regCP_VMID_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5063

RREG32_SOC15(GC, 0, regCP_VMID_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5074

if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) &&

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5075

!RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE))

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5085

grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5098

grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5111

tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5119

if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET))

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5128

tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5181

clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5182

clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5183

clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5185

clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5190

clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5191

clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5192

clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5194

clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5308

rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5324

if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE),

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5344

def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5363

def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5382

def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5405

def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5416

def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5441

def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5457

def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5475

def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5493

def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5502

data = RREG32_SOC15(GC, 0, regCP_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5509

data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5515

data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5521

def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5533

def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5543

data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5549

data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5632

u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5741

data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5758

data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5767

data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5791

wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5792

wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32;

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6711

tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6721

tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6876

reset_pipe = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6911

r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) << 2) -

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

7448

data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

7449

data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

982

return RREG32_SOC15(GC, 0, regSQ_IND_DATA);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

995

*(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0_3.c

91

rlc_status0 = RREG32_SOC15(GC, 0, regRLC_RLCS_FED_STATUS_0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

1345

data = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

1698

gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_CC_GC_SA_UNIT_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

1702

gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_GC_USER_SA_UNIT_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

1717

gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

1721

gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

1789

data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

1920

u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

1939

rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2037

tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2135

tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2157

tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2179

tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2214

tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2256

tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2305

cp_status = RREG32_SOC15(GC, 0, regCP_STAT);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2306

bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2335

u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2342

if (RREG32_SOC15(GC, 0, regCP_STAT) == 0)

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2415

tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2427

tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2440

tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2445

tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2469

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2475

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2480

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2559

tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2571

tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2584

tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2590

tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2614

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2620

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2625

tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2684

tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2695

tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2782

data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2869

tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2875

tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2900

tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2906

tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2919

tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2925

tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2948

tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3277

if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3280

if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3546

gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3582

data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3586

data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3773

tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3803

if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS),

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3818

tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) &

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3914

rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3931

if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE),

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3952

def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4053

def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4069

def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4087

def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4105

def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4114

data = RREG32_SOC15(GC, 0, regCP_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4121

data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4127

data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4133

def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4145

def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4168

def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4179

def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4199

def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4220

def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4286

data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4303

data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4312

data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4336

wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4337

wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32;

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5338

reset_pipe = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5372

r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) << 2) -

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5682

data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5683

data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

821

return RREG32_SOC15(GC, 0, regSQ_IND_DATA);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

834

*(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1128

data = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_THREAD_ENABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1329

gc_disabled_sa_mask = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SA_UNIT_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1333

gc_user_disabled_sa_mask = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SA_UNIT_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1349

gc_disabled_rb_mask = RREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1354

gc_user_disabled_rb_mask = RREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1423

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1428

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_DEBUG);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1497

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1529

u32 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1569

rlc_pg_cntl = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_PG_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1689

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_LX6_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1798

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1852

cp_status = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_STAT);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1853

bootload_status = RREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1894

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2006

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2012

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_BASE_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2039

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2045

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2058

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2064

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2088

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2275

if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) {

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2278

if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2586

gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG_READ);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2623

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2627

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPG_PSP_DEBUG);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2638

val = RREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2656

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_UTCL0_CNTL1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2674

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL3);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2685

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2789

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2834

if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2909

rlc_cntl = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2926

if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3039

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3057

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3076

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3086

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3094

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3118

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3129

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3149

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3170

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3189

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3257

data = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3274

data = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3945

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3946

data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

633

return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

647

*(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

1061

if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

1738

data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

1787

data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

1937

return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

1952

*(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2053

gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2080

gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2090

gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2101

gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2529

data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2530

data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2651

tmp = RREG32_SOC15(GC, 0, mmSQ_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2679

adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2726

if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2748

if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2761

tmp= RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3155

rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3247

u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3436

tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3530

tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3580

tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3587

tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3617

tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3627

tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3654

mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3659

tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3664

tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3670

mqd->cp_hqd_quantum = RREG32_SOC15(GC, 0, mmCP_HQD_QUANTUM);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3704

if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3707

if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3801

if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3806

if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

4005

tmp = RREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

4118

if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

4145

tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

4164

tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

4181

tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

4185

tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

4191

tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

4302

clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

4303

((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

4892

rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

4910

if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

4969

def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

4988

def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

4995

def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

5003

def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

5017

data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

5024

data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

5043

def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

5051

def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

5066

def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

5073

def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

5089

def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

5101

def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

5116

def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

5122

def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

5167

data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

5362

wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

5363

wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

6886

data = RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

6905

data = RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

6926

data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

6939

data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

7039

RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

7044

RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

7049

RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

7054

RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

7299

if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

7831

data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

7832

data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

708

data = RREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

729

data = RREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

752

data = RREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

773

data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

796

data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

942

RREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

947

RREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

952

RREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

957

RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

962

RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1750

data = RREG32_SOC15(GC, 0, regUTCL2_MEM_ECC_STATUS);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1756

data = RREG32_SOC15(GC, 0, regVML2_MEM_ECC_STATUS);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1762

data = RREG32_SOC15(GC, 0, regVML2_WALKER_MEM_ECC_STATUS);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1823

return RREG32_SOC15(GC, 0, regSQ_IND_DATA);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1883

status = RREG32_SOC15(GC, 0,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

757

data = RREG32_SOC15(GC, 0, regSQ_CONFIG1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1244

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1292

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_CONFIG1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1352

RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1393

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1403

rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1421

if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1476

if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0)

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1500

if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1513

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1583

rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1807

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1853

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1860

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1893

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1903

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1930

mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1935

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1940

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1946

mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1981

if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) {

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1984

if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2078

if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) {

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2083

if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2407

if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2434

tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2453

tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2466

tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2470

tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2476

tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2563

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2585

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2607

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2621

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2628

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2636

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2647

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2654

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2671

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2683

def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2695

def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2701

def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

308

if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3466

if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3504

reset_pipe = RREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4503

data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4877

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4878

data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4945

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

515

clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) |

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

516

((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

723

return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

738

*(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

792

xcp_ctl = RREG32_SOC15(GC, GET_INST(GC, 0), regCP_HYP_XCP_CTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

111

u64 base = RREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

121

return (u64)RREG32_SOC15(GC, 0, regGCMC_VM_FB_OFFSET) << 24;

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

192

tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

218

tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

231

tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

262

tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

395

tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

418

tmp = RREG32_SOC15(GC, 0, regCP_DEBUG);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

428

tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

113

u64 base = RREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

123

return (u64)RREG32_SOC15(GC, 0, regGCMC_VM_FB_OFFSET) << 24;

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

197

tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

223

tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

236

tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

267

tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

400

tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

423

tmp = RREG32_SOC15(GC, 0, regCP_DEBUG);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

433

tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

200

tmp = RREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

253

tmp = RREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

288

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regGCVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

307

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regGCVM_L2_CNTL2);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

348

tmp = RREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

43

base = RREG32_SOC15(GC, GET_INST(GC, 0),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

49

RREG32_SOC15(GC, GET_INST(GC, 0),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

542

tmp = RREG32_SOC15(GC, GET_INST(GC, j),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

553

tmp = RREG32_SOC15(GC, GET_INST(GC, j), regGCVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

56

return (u64)(RREG32_SOC15(GC, GET_INST(GC, 0),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

576

tmp = RREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

628

tmp = RREG32_SOC15(GC, GET_INST(GC, i),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

818

xgmi_lfb_cntl = RREG32_SOC15(GC, GET_INST(GC, 0),

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

820

seg_size = REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, 0),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

159

tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

179

tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

190

tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

222

tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

357

tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

36

return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24;

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

381

tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c

53

xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL_ALDE);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c

55

RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE_ALDE),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c

60

xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.c

62

RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE),

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

176

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL2);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

204

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

230

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

241

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_CNTL2);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

278

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_CONTEXT0_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

39

return (u64)RREG32_SOC15(GC, GET_INST(GC, 0), regMC_VM_FB_OFFSET) << 24;

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

460

tmp = RREG32_SOC15(GC, GET_INST(GC, j), regMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

470

tmp = RREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

494

tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

601

xgmi_lfb_cntl = RREG32_SOC15(GC, GET_INST(GC, 0), regMC_VM_XGMI_LFB_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

603

RREG32_SOC15(GC, GET_INST(GC, 0), regMC_VM_XGMI_LFB_SIZE),

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

107

u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

117

return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24;

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

191

tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

214

tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

227

tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

258

tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

373

tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

397

tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

110

u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

120

return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24;

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

195

tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

220

tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

233

tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

264

tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

397

tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

428

tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

522

efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

527

vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

553

adev->gmc.VM_L2_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

554

adev->gmc.VM_L2_CNTL2 = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

555

adev->gmc.VM_DUMMY_PAGE_FAULT_CNTL = RREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

556

adev->gmc.VM_DUMMY_PAGE_FAULT_ADDR_LO32 = RREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

557

adev->gmc.VM_DUMMY_PAGE_FAULT_ADDR_HI32 = RREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

558

adev->gmc.VM_L2_PROTECTION_FAULT_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

559

adev->gmc.VM_L2_PROTECTION_FAULT_CNTL2 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL2);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

560

adev->gmc.VM_L2_PROTECTION_FAULT_MM_CNTL3 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

561

adev->gmc.VM_L2_PROTECTION_FAULT_MM_CNTL4 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

562

adev->gmc.VM_L2_PROTECTION_FAULT_ADDR_LO32 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

563

adev->gmc.VM_L2_PROTECTION_FAULT_ADDR_HI32 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

564

adev->gmc.VM_DEBUG = RREG32_SOC15(GC, 0, mmGCVM_DEBUG);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

565

adev->gmc.VM_L2_MM_GROUP_RT_CLASSES = RREG32_SOC15(GC, 0, mmGCVM_L2_MM_GROUP_RT_CLASSES);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

566

adev->gmc.VM_L2_BANK_SELECT_RESERVED_CID = RREG32_SOC15(GC, 0, mmGCVM_L2_BANK_SELECT_RESERVED_CID);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

567

adev->gmc.VM_L2_BANK_SELECT_RESERVED_CID2 = RREG32_SOC15(GC, 0, mmGCVM_L2_BANK_SELECT_RESERVED_CID2);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

568

adev->gmc.VM_L2_CACHE_PARITY_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_CACHE_PARITY_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

569

adev->gmc.VM_L2_IH_LOG_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_IH_LOG_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

581

adev->gmc.MC_VM_MX_L1_TLB_CNTL = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

642

tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

648

tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

106

u64 base = RREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

116

return (u64)RREG32_SOC15(GC, 0, regGCMC_VM_FB_OFFSET) << 24;

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

189

tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

215

tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

228

tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

259

tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

392

tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

415

tmp = RREG32_SOC15(GC, 0, regCP_DEBUG);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

425

tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

109

u64 base = RREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

119

return (u64)RREG32_SOC15(GC, 0, regGCMC_VM_FB_OFFSET) << 24;

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

194

tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

220

tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

233

tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

264

tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

385

tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

413

tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

526

u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

535

viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

536

pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH);

drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c

517

u32 d1vga_control = RREG32_SOC15(DCE, 0, regD1VGA_CONTROL);

drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c

526

viewport = RREG32_SOC15(DCE, 0, regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);

drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c

527

pitch = RREG32_SOC15(DCE, 0, regHUBPREQ0_DCSURF_SURFACE_PITCH);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

1314

u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

1327

viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

1335

viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

1343

viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

1810

adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

2108

RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0));

drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c

68

err_data->ue_count += RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);

drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c

80

RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);

drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c

144

hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);

drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c

180

tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);

drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c

190

tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);

drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c

203

tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL);

drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c

53

hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);

drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c

54

hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);

drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c

147

hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);

drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c

176

tmp = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);

drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c

186

tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);

drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c

65

hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);

drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c

66

hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);

drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c

131

tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);

drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c

45

hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1);

drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c

47

hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);

drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c

48

hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);

drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c

119

tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);

drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c

41

hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0,regHDP_CLK_CNTL);

drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c

42

hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

339

ih_chicken = RREG32_SOC15(OSSSYS, 0, regIH_CHICKEN);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

359

tmp = RREG32_SOC15(OSSSYS, 0, regIH_STORM_CLIENT_LIST_CNTL);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

364

tmp = RREG32_SOC15(OSSSYS, 0, regIH_INT_FLOOD_CNTL);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

373

tmp = RREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

380

tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

384

tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

682

def = data = RREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

715

ih_mem_pwr_cntl = RREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

778

if (!RREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL))

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

98

ih_cntl = RREG32_SOC15(OSSSYS, 0, regIH_CNTL2);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

99

ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

311

ih_chicken = RREG32_SOC15(OSSSYS, 0, regIH_CHICKEN);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

330

tmp = RREG32_SOC15(OSSSYS, 0, regIH_STORM_CLIENT_LIST_CNTL);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

335

tmp = RREG32_SOC15(OSSSYS, 0, regIH_INT_FLOOD_CNTL);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

344

tmp = RREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

351

tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

355

tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

657

def = data = RREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

692

ih_mem_pwr_cntl = RREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

755

if (!RREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL))

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

98

ih_cntl = RREG32_SOC15(OSSSYS, 0, regIH_CNTL2);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

99

ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

321

ih_chicken = RREG32_SOC15(OSSSYS, 0, regIH_CHICKEN);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

340

tmp = RREG32_SOC15(OSSSYS, 0, regIH_STORM_CLIENT_LIST_CNTL);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

345

tmp = RREG32_SOC15(OSSSYS, 0, regIH_INT_FLOOD_CNTL);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

354

tmp = RREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

361

tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

365

tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

383

tmp = RREG32_SOC15(OSSSYS, 0, regIH_RETRY_INT_CAM_CNTL);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

675

def = data = RREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

710

ih_mem_pwr_cntl = RREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

773

if (!RREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL))

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

98

ih_cntl = RREG32_SOC15(OSSSYS, 0, regIH_CNTL2);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

99

ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1);

drivers/gpu/drm/amd/amdgpu/imu_v11_0.c

136

imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL);

drivers/gpu/drm/amd/amdgpu/imu_v11_0.c

159

imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16);

drivers/gpu/drm/amd/amdgpu/imu_v11_0.c

165

imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10);

drivers/gpu/drm/amd/amdgpu/imu_v11_0.c

175

imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL);

drivers/gpu/drm/amd/amdgpu/imu_v11_0.c

382

reg_data = RREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX);

drivers/gpu/drm/amd/amdgpu/imu_v12_0.c

130

imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL);

drivers/gpu/drm/amd/amdgpu/imu_v12_0.c

152

imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16);

drivers/gpu/drm/amd/amdgpu/imu_v12_0.c

156

imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10);

drivers/gpu/drm/amd/amdgpu/imu_v12_0.c

167

imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL);

drivers/gpu/drm/amd/amdgpu/imu_v12_0.c

309

return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE);

drivers/gpu/drm/amd/amdgpu/imu_v12_0.c

311

return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_TOP);

drivers/gpu/drm/amd/amdgpu/imu_v12_0.c

313

return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET);

drivers/gpu/drm/amd/amdgpu/imu_v12_0.c

315

return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE);

drivers/gpu/drm/amd/amdgpu/imu_v12_0.c

317

return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT);

drivers/gpu/drm/amd/amdgpu/imu_v12_0.c

319

return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP);

drivers/gpu/drm/amd/amdgpu/imu_v12_0.c

321

return RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/imu_v12_0.c

323

return RREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR);

drivers/gpu/drm/amd/amdgpu/imu_v12_0.c

325

return RREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR);

drivers/gpu/drm/amd/amdgpu/imu_v12_0.c

327

return RREG32_SOC15(MMHUB, 0, regMMMC_VM_LOCAL_FB_ADDRESS_START);

drivers/gpu/drm/amd/amdgpu/imu_v12_0.c

329

return RREG32_SOC15(MMHUB, 0, regMMMC_VM_LOCAL_FB_ADDRESS_END);

drivers/gpu/drm/amd/amdgpu/imu_v12_0.c

331

return RREG32_SOC15(MMHUB, 0, regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START);

drivers/gpu/drm/amd/amdgpu/imu_v12_0.c

333

return RREG32_SOC15(MMHUB, 0, regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END);

drivers/gpu/drm/amd/amdgpu/imu_v12_0.c

335

return RREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB);

drivers/gpu/drm/amd/amdgpu/imu_v12_0.c

337

return RREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB);

drivers/gpu/drm/amd/amdgpu/imu_v12_0.c

394

reg_data = RREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX);

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

144

return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

158

return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c

547

ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c

183

RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))

drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c

286

data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c

296

data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c

309

data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c

319

data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c

372

ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c

418

return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c

435

return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c

689

return ((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &

drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c

249

RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS))

drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c

303

data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c

313

data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c

320

data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c

332

data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c

376

ring->wptr = RREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c

446

return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c

463

return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c

530

ret &= (((RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS) &

drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c

819

reg_value = RREG32_SOC15(JPEG, instance, mmUVD_RAS_JPEG0_STATUS);

drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c

82

harvest = RREG32_SOC15(JPEG, i, mmCC_UVD_HARVESTING);

drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c

823

reg_value = RREG32_SOC15(JPEG, instance, mmUVD_RAS_JPEG1_STATUS);

drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c

198

RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))

drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c

248

data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c

258

data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c

266

data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c

278

data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c

392

ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c

437

return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c

454

return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c

481

ret &= (((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &

drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c

76

harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c

227

RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c

280

data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c

292

data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c

304

data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c

316

data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c

428

ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c

461

header.total_size = RREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c

509

tmp = RREG32_SOC15(VCN, 0, regMMSCH_VF_VMID);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c

533

resp = RREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c

597

return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c

614

return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c

641

ret &= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS) &

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c

828

reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG0_STATUS);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c

832

reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG1_STATUS);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1351

reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG0_STATUS);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

1355

reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG1_STATUS);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

322

tmp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

341

resp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

392

if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) &

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

499

data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

511

data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

524

data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

536

data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c

260

RREG32_SOC15(JPEG, i, regUVD_JRBC_STATUS))

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c

311

data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c

323

data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c

335

data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c

347

data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c

427

reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c

440

reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c

473

ring->wptr = RREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c

488

reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c

558

ring->wptr = RREG32_SOC15(JPEG, i, regUVD_JRBC_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c

613

return RREG32_SOC15(JPEG, ring->me, regUVD_JRBC_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c

630

return RREG32_SOC15(JPEG, ring->me, regUVD_JRBC_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c

661

ret &= (((RREG32_SOC15(JPEG, i, regUVD_JRBC_STATUS) &

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c

194

RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c

246

data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c

256

data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c

261

data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c

349

reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c

396

ring->wptr = RREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c

413

reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c

473

ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c

523

return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c

540

return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c

567

ret &= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS) &

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

271

if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100)

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

520

tmp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

539

resp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

971

reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG0_STATUS);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

975

reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG1_STATUS);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c

177

RREG32_SOC15(JPEG, 0, regUVD_JRBC0_UVD_JRBC_STATUS))

drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c

229

data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c

239

data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c

244

data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c

332

reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c

379

ring->wptr = RREG32_SOC15(JPEG, inst_idx, regUVD_JRBC0_UVD_JRBC_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c

396

reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c

456

ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c

506

return RREG32_SOC15(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c

523

return RREG32_SOC15(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c

550

ret &= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC0_UVD_JRBC_STATUS) &

drivers/gpu/drm/amd/amdgpu/lsdma_v6_0.c

109

tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_MEM_POWER_CTRL);

drivers/gpu/drm/amd/amdgpu/lsdma_v6_0.c

55

tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND);

drivers/gpu/drm/amd/amdgpu/lsdma_v6_0.c

87

tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND);

drivers/gpu/drm/amd/amdgpu/lsdma_v7_0.c

109

tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_MEM_POWER_CTRL);

drivers/gpu/drm/amd/amdgpu/lsdma_v7_0.c

55

tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND);

drivers/gpu/drm/amd/amdgpu/lsdma_v7_0.c

87

tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1068

data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1074

data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1224

data = RREG32_SOC15(GC, 0, regCP_HQD_VMID);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1229

data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1239

data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1523

if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1526

if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1531

data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1554

tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1565

tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

425

if (!(RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

446

if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

939

RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

942

RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

961

RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI),

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

962

RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO));

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

965

data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

999

data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1107

RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI),

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1108

RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO));

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1112

data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1144

data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1228

data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1234

data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1389

data = RREG32_SOC15(GC, 0, regCP_HQD_VMID);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1394

data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1404

data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1506

adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1508

adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1701

if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1704

if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1709

data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1734

tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

395

val = RREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

448

if (!(RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

469

if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

813

data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

822

data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

831

data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

840

data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

849

data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

867

uint32_t data = RREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1010

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1043

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1129

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1135

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1315

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1320

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1330

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1431

adev->mes.sched_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1433

adev->mes.kiq_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1656

if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) {

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1659

if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1664

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1689

tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

747

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL1);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

756

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL2);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

765

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL3);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

774

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL4);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

783

data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL5);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

801

uint32_t data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_UNMAPPED_DOORBELL);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

131

tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

142

tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

165

tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

176

tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

203

tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

262

tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXT0_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

272

tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CNTL4);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

39

u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

40

u64 top = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

402

tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

412

tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

432

tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

503

def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

506

def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

507

def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

509

def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

566

def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

608

data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

610

data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

149

tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL2);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

160

tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

207

tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

218

tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL2);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

254

tmp = RREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

386

tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

39

u64 base = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

396

tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

40

u64 top = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

416

tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

486

def = data = RREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

488

def1 = data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

489

def2 = data2 = RREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

540

def = data = RREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

577

data = RREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

579

data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

186

tmp = RREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL2);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

199

tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

217

tmp = RREG32_SOC15(MMHUB, i, regMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

276

tmp = RREG32_SOC15(MMHUB, i, regVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

291

tmp = RREG32_SOC15(MMHUB, i, regVM_L2_CNTL2);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

333

tmp = RREG32_SOC15(MMHUB, i, regVM_CONTEXT0_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

40

u64 base = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

41

u64 top = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

486

tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

494

tmp = RREG32_SOC15(MMHUB, i, regMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

519

tmp = RREG32_SOC15(MMHUB, j, regVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

546

tmp = RREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

252

tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

263

tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

288

tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

301

tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

332

tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

457

tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

464

tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

486

tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

578

def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

581

def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

582

def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

638

def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

690

data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

693

data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

694

data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

180

tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

191

tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

210

tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

223

tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

254

tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

387

tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

394

tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

411

tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

498

def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_CGTT_CLK_CTRL);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

499

def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

532

def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_CGTT_CLK_CTRL);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

533

def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_WR_CGTT_CLK_CTRL);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

534

def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB0_RD_CGTT_CLK_CTRL);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

591

data = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

592

data1 = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_CGTT_CLK_CTRL);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

593

data2 = RREG32_SOC15(MMHUB, 0, mmDAGB0_WR_CGTT_CLK_CTRL);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

594

data3 = RREG32_SOC15(MMHUB, 0, mmDAGB0_RD_CGTT_CLK_CTRL);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

205

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

216

tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

242

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

255

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

286

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

411

tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

418

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

440

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

530

base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

540

return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24;

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

551

def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

553

def1 = data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

554

def2 = data2 = RREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

609

def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

644

data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

211

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

222

tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

242

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

255

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

286

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

405

tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

412

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

429

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

513

base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

522

return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24;

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

530

def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

546

def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

577

data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

197

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

208

tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

234

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

247

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

278

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

403

tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

410

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

432

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

519

base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

528

return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24;

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

337

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

348

tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

368

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

381

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

412

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

525

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

535

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CNTL4);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

581

tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

588

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

605

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

689

base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

700

offset = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

712

def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

728

def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

759

data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

198

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

209

tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

235

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

248

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

279

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

404

tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

411

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

434

tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

524

base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

534

return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24;

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

546

def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

548

def1 = data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

549

def2 = data2 = RREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

589

def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

626

data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

246

tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

297

tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

329

tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

345

tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL2);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

393

tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

560

tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, j),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

570

tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, j), regMMVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

599

tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

79

base = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

796

def = data = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regMM_ATC_L2_MISC_CG);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

797

def1 = data1 = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regDAGB0_CNTL_MISC2);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

798

def2 = data2 = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regDAGB1_CNTL_MISC2);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

831

def = data = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regMM_ATC_L2_MISC_CG);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

85

RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0),

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

866

data = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regMM_ATC_L2_MISC_CG);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

93

return (u64)RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0),

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

42

u64 base = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE);

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

43

u64 top = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP);

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

697

data = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG);

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

699

data1 = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG);

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

113

ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2);

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

114

ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

130

ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

337

ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid);

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

343

ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

652

def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL);

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

689

if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL))

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

141

doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL);

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

143

doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL);

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

229

u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL);

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

272

interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL);

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

352

data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2);

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

361

data = RREG32_SOC15(NBIO, 0, regREGS_ROM_OFFSET_CTRL);

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

373

def = RREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL);

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

380

def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2);

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

403

def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL);

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

410

def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL7);

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

415

def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3);

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

420

def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3);

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

426

def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5);

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

445

def = data = RREG32_SOC15(NBIO, 0, regPSWUSP0_PCIE_LC_CNTL2);

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

452

def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL4);

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

457

def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL);

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

464

def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3);

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

470

def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5);

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

475

def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL);

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

482

def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3);

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

540

bif_doorbell_int_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

570

bif_doorbell_int_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

68

u32 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

88

return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE);

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

97

u32 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL);

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

105

return RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE);

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

189

u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE);

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

213

interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

386

def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP2);

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

430

def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3);

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

436

def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5);

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

466

def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3);

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

472

def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5);

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

538

reg = RREG32_SOC15(NBIO, 0, mmBIF_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

543

reg = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

86

tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

108

doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_5_CTRL);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

110

doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_4_CTRL);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

184

u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_1_CTRL);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

223

interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

246

def = data = RREG32_SOC15(NBIO, 0, regCPM_CONTROL);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

276

def = data = RREG32_SOC15(NBIO, 0, regPCIE_CNTL2);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

293

data = RREG32_SOC15(NBIO, 0, regCPM_CONTROL);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

298

data = RREG32_SOC15(NBIO, 0, regPCIE_CNTL2);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

343

data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

353

data = RREG32_SOC15(NBIO, 0, regREGS_ROM_OFFSET_CTRL);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

364

def = RREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

371

def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

376

def = data = RREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

395

def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

402

def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL7);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

407

def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

41

u32 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

412

def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

418

def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

423

def = data = RREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

430

def = data = RREG32_SOC15(NBIO, 0, regPSWUSP0_PCIE_LC_CNTL2);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

437

def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL4);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

442

def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

449

def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

455

def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

460

def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

467

def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

569

bif_doorbell_int_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

599

bif_doorbell_int_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

61

return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

69

u32 doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_2_CTRL);

drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

135

u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE);

drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

153

interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

65

u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);

drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

85

return RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE);

drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c

119

u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE);

drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c

135

data = RREG32_SOC15(NBIO, 0, mmSYSHUB_DATA);

drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c

228

interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c

282

data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF6_STRAP4) & ~BIT(23);

drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c

45

u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);

drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c

64

return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

142

reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN);

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

177

u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0,regGDC0_BIF_IH_DOORBELL_RANGE);

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

204

interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

268

def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3);

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

283

data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF5_STRAP4) & ~BIT(23);

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

297

def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL);

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

326

def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2);

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

335

def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1);

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

354

data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL);

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

359

data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2);

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

42

tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0);

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

61

return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE);

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

104

return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE);

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

155

reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN);

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

218

interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

399

data = RREG32_SOC15(NBIO, 0, regRCC_DEV2_EPF0_STRAP2);

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

65

tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC);

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

68

tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

114

tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0_ALDE);

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

116

tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

135

return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

236

u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

296

interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

347

baco_cntl = RREG32_SOC15(NBIO, 0, mmBACO_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

370

bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE);

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

372

bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

427

bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE);

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

429

bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

460

bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE);

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

462

bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

505

bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE);

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

507

bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

112

reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN);

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

148

u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0,

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

176

interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

240

def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3);

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

251

data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF5_STRAP4) & ~BIT(23);

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

265

def = data = RREG32_SOC15(NBIO, 0, regBIF0_CPM_CONTROL);

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

294

def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_CNTL2);

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

303

def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_TX_POWER_CTRL_1);

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

322

data = RREG32_SOC15(NBIO, 0, regBIF0_CPM_CONTROL);

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

327

data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_CNTL2);

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

42

tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

61

return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE);

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

330

interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

399

tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_STATUS);

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

410

tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_STATUS);

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

422

tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_STATUS);

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

427

RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_CAP);

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

453

baco_cntl = RREG32_SOC15(NBIO, i, regBIF_BX0_BACO_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

528

bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

53

rev_id = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

574

bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL);

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

72

return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE);

drivers/gpu/drm/amd/amdgpu/nv.c

552

sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);

drivers/gpu/drm/amd/amdgpu/psp_v10_0.c

151

return RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);

drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

153

sol_reg1 = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);

drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

155

sol_reg2 = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);

drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

160

RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_33),

drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

161

RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81));

drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

196

sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);

drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

278

RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 0,

drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

592

data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);

drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

633

reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35);

drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

662

*fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36);

drivers/gpu/drm/amd/amdgpu/psp_v11_0_8.c

156

data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);

drivers/gpu/drm/amd/amdgpu/psp_v11_0_8.c

158

data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);

drivers/gpu/drm/amd/amdgpu/psp_v12_0.c

115

sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);

drivers/gpu/drm/amd/amdgpu/psp_v12_0.c

136

RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 0,

drivers/gpu/drm/amd/amdgpu/psp_v12_0.c

258

data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);

drivers/gpu/drm/amd/amdgpu/psp_v12_0.c

260

data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);

drivers/gpu/drm/amd/amdgpu/psp_v12_0.c

79

sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);

drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

147

sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);

drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

335

psp->sos.fw_version = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_58);

drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

371

RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 0,

drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

505

data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);

drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

507

data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);

drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

702

reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35);

drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

731

*fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36);

drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

762

reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);

drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

842

return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);

drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

854

reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);

drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

884

reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_127);

drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c

186

RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 0,

drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c

317

data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);

drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c

319

data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);

drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c

64

sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);

drivers/gpu/drm/amd/amdgpu/psp_v14_0.c

233

RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81), 0,

drivers/gpu/drm/amd/amdgpu/psp_v14_0.c

364

data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102);

drivers/gpu/drm/amd/amdgpu/psp_v14_0.c

366

data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67);

drivers/gpu/drm/amd/amdgpu/psp_v14_0.c

562

reg_status = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35);

drivers/gpu/drm/amd/amdgpu/psp_v14_0.c

592

*fw_ver = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36);

drivers/gpu/drm/amd/amdgpu/psp_v14_0.c

626

reg_status = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_115);

drivers/gpu/drm/amd/amdgpu/psp_v14_0.c

676

return RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_115);

drivers/gpu/drm/amd/amdgpu/psp_v14_0.c

99

sol_reg = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81);

drivers/gpu/drm/amd/amdgpu/psp_v15_0.c

175

data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102);

drivers/gpu/drm/amd/amdgpu/psp_v15_0.c

177

data = RREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_67);

drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c

171

data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102);

drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c

173

data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67);

drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c

203

reg_data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_127);

drivers/gpu/drm/amd/amdgpu/psp_v3_1.c

127

sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);

drivers/gpu/drm/amd/amdgpu/psp_v3_1.c

150

RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 0,

drivers/gpu/drm/amd/amdgpu/psp_v3_1.c

349

data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);

drivers/gpu/drm/amd/amdgpu/psp_v3_1.c

88

sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1340

tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1344

tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1350

tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

776

tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

780

tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

786

tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

783

tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

788

tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

775

tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

780

tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

766

tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

771

tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

108

RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_INTR);

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

187

reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

195

reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_INTR_STAT);

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

198

reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE);

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

232

reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE);

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

251

reg_ic_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

300

reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

424

reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD);

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

469

reg_ic_enable_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE_STATUS);

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

470

reg_ic_enable = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE);

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

486

reg_ic_clr_activity = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_ACTIVITY);

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

51

uint32_t reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT);

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

531

status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

532

enable = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE);

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

533

en_stat = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE_STATUS);

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

87

u32 en_stat = RREG32_SOC15(SMUIO,

drivers/gpu/drm/amd/amdgpu/smuio_v11_0.c

49

def = data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0);

drivers/gpu/drm/amd/amdgpu/smuio_v11_0.c

70

data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0);

drivers/gpu/drm/amd/amdgpu/smuio_v11_0_6.c

46

def = data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0);

drivers/gpu/drm/amd/amdgpu/smuio_v11_0_6.c

67

data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0);

drivers/gpu/drm/amd/amdgpu/smuio_v13_0.c

102

data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);

drivers/gpu/drm/amd/amdgpu/smuio_v13_0.c

119

data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);

drivers/gpu/drm/amd/amdgpu/smuio_v13_0.c

136

data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);

drivers/gpu/drm/amd/amdgpu/smuio_v13_0.c

48

def = data = RREG32_SOC15(SMUIO, 0, regCGTT_ROM_CLK_CTRL0);

drivers/gpu/drm/amd/amdgpu/smuio_v13_0.c

69

data = RREG32_SOC15(SMUIO, 0, regCGTT_ROM_CLK_CTRL0);

drivers/gpu/drm/amd/amdgpu/smuio_v13_0.c

85

data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);

drivers/gpu/drm/amd/amdgpu/smuio_v13_0_3.c

42

data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);

drivers/gpu/drm/amd/amdgpu/smuio_v13_0_3.c

59

data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);

drivers/gpu/drm/amd/amdgpu/smuio_v13_0_3.c

78

data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);

drivers/gpu/drm/amd/amdgpu/smuio_v14_0_2.c

45

clock_counter_hi_pre = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);

drivers/gpu/drm/amd/amdgpu/smuio_v14_0_2.c

46

clock_counter_lo = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);

drivers/gpu/drm/amd/amdgpu/smuio_v14_0_2.c

48

clock_counter_hi_after = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);

drivers/gpu/drm/amd/amdgpu/smuio_v14_0_2.c

50

clock_counter_lo = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);

drivers/gpu/drm/amd/amdgpu/smuio_v15_0_0.c

35

clock_counter_hi_pre = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);

drivers/gpu/drm/amd/amdgpu/smuio_v15_0_0.c

36

clock_counter_lo = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);

drivers/gpu/drm/amd/amdgpu/smuio_v15_0_0.c

38

clock_counter_hi_after = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);

drivers/gpu/drm/amd/amdgpu/smuio_v15_0_0.c

40

clock_counter_lo = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);

drivers/gpu/drm/amd/amdgpu/smuio_v15_0_8.c

107

data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);

drivers/gpu/drm/amd/amdgpu/smuio_v15_0_8.c

124

data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);

drivers/gpu/drm/amd/amdgpu/smuio_v15_0_8.c

151

data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);

drivers/gpu/drm/amd/amdgpu/smuio_v15_0_8.c

167

data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);

drivers/gpu/drm/amd/amdgpu/smuio_v15_0_8.c

192

data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);

drivers/gpu/drm/amd/amdgpu/smuio_v15_0_8.c

53

clock_counter_hi_pre = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);

drivers/gpu/drm/amd/amdgpu/smuio_v15_0_8.c

54

clock_counter_lo = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);

drivers/gpu/drm/amd/amdgpu/smuio_v15_0_8.c

56

clock_counter_hi_after = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);

drivers/gpu/drm/amd/amdgpu/smuio_v15_0_8.c

58

clock_counter_lo = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);

drivers/gpu/drm/amd/amdgpu/smuio_v15_0_8.c

74

data = RREG32_SOC15(SMUIO, 0, regCGTT_ROM_CLK_CTRL0);

drivers/gpu/drm/amd/amdgpu/smuio_v15_0_8.c

90

data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);

drivers/gpu/drm/amd/amdgpu/smuio_v9_0.c

46

def = data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0);

drivers/gpu/drm/amd/amdgpu/smuio_v9_0.c

67

data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0);

drivers/gpu/drm/amd/amdgpu/soc15.c

303

r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);

drivers/gpu/drm/amd/amdgpu/soc15.c

325

r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);

drivers/gpu/drm/amd/amdgpu/soc15.c

872

sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);

drivers/gpu/drm/amd/amdgpu/soc21.c

511

sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);

drivers/gpu/drm/amd/amdgpu/soc21.c

988

sol_reg1 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);

drivers/gpu/drm/amd/amdgpu/soc21.c

990

sol_reg2 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);

drivers/gpu/drm/amd/amdgpu/soc24.c

280

sol_reg = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81);

drivers/gpu/drm/amd/amdgpu/soc_v1_0.c

225

sol_reg = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

129

data = RREG32_SOC15(VCN, 0, regUVD_UMSCH_FORCE);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

134

data = RREG32_SOC15(VCN, 0, regVCN_MES_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

139

data = RREG32_SOC15(VCN, 0, regVCN_MES_IC_OP_CNTL);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

154

data = RREG32_SOC15(VCN, 0, regVCN_MES_CNTL);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

167

RREG32_SOC15(VCN, 0, regVCN_MES_MSTATUS_LO));

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

189

data = RREG32_SOC15(VCN, 0, regVCN_AGDB_CTRL0);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

195

data = RREG32_SOC15(VCN, 0, regVCN_AGDB_CTRL1);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

201

data = RREG32_SOC15(VCN, 0, regVCN_AGDB_CTRL2);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

207

data = RREG32_SOC15(VCN, 0, regVCN_AGDB_CTRL3);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

220

data = RREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_DB_CTRL);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

235

data = RREG32_SOC15(VCN, 0, regVCN_RB_ENABLE);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

250

data = RREG32_SOC15(VCN, 0, regVCN_RB_ENABLE);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

254

data = RREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_DB_CTRL);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

72

data = RREG32_SOC15(VCN, 0, regUMSCH_MES_RESET_CTRL);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

76

data = RREG32_SOC15(VCN, 0, regVCN_MES_CNTL);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

83

data = RREG32_SOC15(VCN, 0, regVCN_MES_IC_BASE_CNTL);

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

1051

status = RREG32_SOC15(UVD, k, mmUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

106

return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

1110

ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

124

return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

126

return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2);

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

1269

tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID);

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

376

harvest = RREG32_SOC15(UVD, i, mmUVD_PG0_CC_UVD_HARVESTING);

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

748

data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID);

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

75

return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

770

data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP);

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

774

data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP);

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

90

return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

92

return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1015

RREG32_SOC15(UVD, 0, mmUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1033

tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1153

ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1165

RREG32_SOC15(UVD, 0, mmUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1233

RREG32_SOC15(UVD, 0, mmUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1249

tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1252

tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1255

tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1258

tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1272

RREG32_SOC15(UVD, 0, mmUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1307

reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1342

RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1362

reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1375

reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1402

RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1422

return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1466

return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1480

return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1673

return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1675

return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1690

return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1692

return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

2017

adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

286

RREG32_SOC15(VCN, 0, mmUVD_STATUS))) {

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

502

data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

513

data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

518

data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

528

data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

551

data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

575

data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

602

data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

629

data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

638

data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

643

data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

652

data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

675

data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

783

data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

798

data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

853

tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

864

tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

877

tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

903

RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0) | 0x3);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

916

tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

925

status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

959

tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY;

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

989

ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1019

tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1034

tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1042

tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1077

tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1094

status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1149

ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1175

RREG32_SOC15(UVD, 0, mmUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1192

tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1195

tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1198

tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1211

RREG32_SOC15(UVD, 0, mmUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1243

tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1281

RREG32_SOC15(VCN, 0, mmUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1303

reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1348

RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1383

return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1429

return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1446

return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1655

return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1657

return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1675

return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1680

return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1909

data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1936

data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1940

data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

328

RREG32_SOC15(VCN, 0, mmUVD_STATUS)))

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

552

data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

561

data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

584

data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

608

data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

635

data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

714

data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

723

data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

746

data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

801

data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

820

data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

864

tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

984

ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

996

RREG32_SOC15(UVD, 0, mmUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1012

tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1139

ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1151

RREG32_SOC15(VCN, inst_idx, mmUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1180

tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1198

tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1207

tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1255

status = RREG32_SOC15(VCN, i, mmUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1315

ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1341

RREG32_SOC15(VCN, i, mmUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1364

data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1382

data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1386

data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1553

tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1556

tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1559

tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1572

RREG32_SOC15(VCN, inst_idx, mmUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1606

tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1643

RREG32_SOC15(VCN, i, mmUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1664

reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) &

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1739

return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1756

return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1821

return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1823

return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1841

return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1846

return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1953

ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

2163

reg_value = RREG32_SOC15(VCN, instance, mmUVD_RAS_VCPU_VCODEC_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

239

harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

521

RREG32_SOC15(VCN, i, mmUVD_STATUS)))

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

759

data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

768

data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

794

data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

818

data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

845

data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

925

data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

934

data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

956

data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1005

data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1041

tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1170

ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1188

RREG32_SOC15(VCN, inst_idx, mmUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1215

tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1233

tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1239

tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1247

tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1290

status = RREG32_SOC15(VCN, i, mmUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1350

ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1380

RREG32_SOC15(VCN, i, mmUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1553

tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1576

resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1608

tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1611

tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1614

tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1627

RREG32_SOC15(VCN, inst_idx, mmUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1661

tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1685

tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1688

tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1704

RREG32_SOC15(VCN, i, mmUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1727

reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) &

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1807

return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1824

return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

2065

return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

2067

return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

2085

return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

2090

return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

2204

ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

2241

if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE)

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

456

RREG32_SOC15(VCN, i, mmUVD_STATUS))) {

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

715

data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

732

data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

785

data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

794

data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

820

data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

843

data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

877

data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

885

data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

973

data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

982

data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1009

tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1100

tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1107

tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1109

ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1111

tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1123

RREG32_SOC15(VCN, inst_idx, regUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1160

tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1178

tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1184

tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1192

tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1235

status = RREG32_SOC15(VCN, i, regUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1290

tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1297

tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1299

ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1301

tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1309

RREG32_SOC15(VCN, i, regUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1515

tmp = RREG32_SOC15(VCN, 0, regMMSCH_VF_VMID);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1538

resp = RREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1582

tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1595

RREG32_SOC15(VCN, inst_idx, regUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1638

tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1662

tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1665

tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1681

RREG32_SOC15(VCN, i, regUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1710

reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) &

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1755

return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

1775

return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

2049

ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

2102

if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

2269

reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

381

RREG32_SOC15(VCN, i, regUVD_STATUS))) {

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

666

data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

692

data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

750

data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

756

data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

781

data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

804

data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

831

data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

921

data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

927

data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

950

data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1139

tmp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1156

resp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1204

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) |

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1224

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1230

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1238

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1283

status = RREG32_SOC15(VCN, vcn_inst,

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1335

tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1343

tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1347

ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1379

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1392

RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1438

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1463

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1467

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1480

RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1506

reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) &

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1548

return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1568

return RREG32_SOC15(VCN, GET_INST(VCN, ring->me),

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1731

if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100)

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1821

ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) ==

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

1868

if (RREG32_SOC15(VCN, GET_INST(VCN, i),

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

2098

reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

311

RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

345

if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) &

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

656

data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

662

data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

679

data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

694

data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

718

data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

803

data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

809

data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

823

data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

860

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

968

tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

976

ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

978

tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

989

RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1013

tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1020

tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1022

ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1024

tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1035

RREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1072

tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1090

tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1096

tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1104

tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1147

status = RREG32_SOC15(VCN, i, regUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1203

tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1210

tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1212

ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1214

tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1221

RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1244

tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1257

RREG32_SOC15(VCN, inst_idx, regUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1301

tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1325

tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1328

tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1344

RREG32_SOC15(VCN, i, regUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1373

reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) &

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1419

return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1439

return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1551

ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

1604

if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

334

RREG32_SOC15(VCN, i, regUVD_STATUS))) {

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

620

data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

643

data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

688

data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

694

data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

719

data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

742

data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

769

data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

859

data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

865

data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

888

data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c

924

tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

1032

tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

1056

tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

1059

tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

1072

RREG32_SOC15(VCN, i, regUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

1101

reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) &

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

1143

return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

1163

return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

1272

ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

1325

if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

298

RREG32_SOC15(VCN, i, regUVD_STATUS))) {

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

587

data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

612

data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

709

tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

770

tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

777

tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

779

ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

781

tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

793

RREG32_SOC15(VCN, inst_idx, regUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

829

tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

844

tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

850

tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

875

status = RREG32_SOC15(VCN, i, regUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

931

tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

938

tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

940

ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

942

tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

950

RREG32_SOC15(VCN, i, regUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

976

tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

986

RREG32_SOC15(VCN, inst_idx, regUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1010

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1016

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1041

status = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1095

RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1101

tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1108

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1110

ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1112

tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1120

RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1150

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1160

RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1202

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1226

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1229

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1239

RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1258

return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1278

return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1481

ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) == UVD_STATUS__IDLE);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1527

if (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) != UVD_STATUS__IDLE)

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

1684

reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

316

if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100)

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

634

reg_data = RREG32_SOC15(VCN, vcn_inst, regUVD_DPG_PAUSE) &

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

685

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

756

tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

763

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

765

ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

767

tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

777

RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

927

tmp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

944

resp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

995

tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

276

ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

583

def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

324

ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

338

ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

683

def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

647

gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

1294

uint32_t reg_value = RREG32_SOC15(THM, 0, mmTHM_TCON_CUR_TMP);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

339

reg = RREG32_SOC15(PWR, 0, mmPWR_MISC_CNTL_STATUS);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu9_baco.c

43

reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu9_baco.c

57

reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

4009

val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_PLANE0_CURRENTVID) &

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

943

data->mem_channels = (RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0) &

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

104

REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

132

REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

135

REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

141

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

144

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

161

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

165

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

263

duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

274

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

322

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

339

temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

389

val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

415

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

421

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

74

duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

76

duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c

150

temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c

189

val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.c

48

reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.c

62

reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.c

87

data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c

2280

val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

124

duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

126

duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

152

duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

163

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

206

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

223

temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

260

val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

95

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

98

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

drivers/gpu/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c

59

return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);

drivers/gpu/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c

76

return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);

drivers/gpu/drm/amd/pm/powerplay/smumgr/smu9_smumgr.c

171

return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_102);

drivers/gpu/drm/amd/pm/powerplay/smumgr/smu9_smumgr.c

173

return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);

drivers/gpu/drm/amd/pm/powerplay/smumgr/smu9_smumgr.c

74

return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_103);

drivers/gpu/drm/amd/pm/powerplay/smumgr/smu9_smumgr.c

83

return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);

drivers/gpu/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

155

return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);

drivers/gpu/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c

80

return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1115

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT),

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1118

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT),

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1155

tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS_ARCT);

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1178

duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT),

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1188

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0_ARCT),

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1210

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT),

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1235

duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT),

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1237

duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS_ARCT),

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

452

val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

372

val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2490

val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

371

val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1044

val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1166

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1169

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1184

duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1194

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1223

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1248

duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1250

duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS),

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1283

tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS);

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1346

val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1354

val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1366

val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1382

val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT);

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1387

val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1442

data = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1632

data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT);

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1636

data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

89

data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

2312

reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_GFX_MISC_CNTL);

drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c

150

reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_GFX_MISC_CNTL);

drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

1908

val = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1045

val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) &

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1087

REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1090

REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1108

duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1),

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1118

REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0),

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1169

REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1199

val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1207

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1219

val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1235

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1240

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1302

data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1340

data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1353

data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1807

data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1857

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1864

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1869

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

636

reg = RREG32_SOC15(SMUIO, 0, regSMUIO_GFX_MISC_CNTL);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

1008

data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

875

val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

884

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

888

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

900

val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

917

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_mp1_14_0_0);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

922

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

926

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

931

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

980

data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

995

data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

841

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_15_0_0);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

845

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

854

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_mp1_15_0_0);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

859

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_15_0_0);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

863

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

868

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);